臺灣博碩士論文加值系統

提出一個改善CMOS電壓對電流轉換器的方法，使用兩個PMOS電晶體取代傳統電壓對電流轉換器的電阻，這兩個電晶體分別操作在三極區及飽和區，並且使用電流鏡結合它們的汲極電流，產生一個與輸入電壓具有線性關係的輸出電流。因為替代電阻採用PMOS電晶體及電壓準位轉移技術，對於先前已公開發表的轉換器[10]電路中，主要由NMOS電晶體產生的基板效應，造成轉換器大信號轉阻的非線性，已經被大大地最小化。為了準確地消除非線性電壓項，必須採用一個操作在線性區汲-源極電流較好的模型，特別地，在我們的設計中更認真仔細地探討電晶體基板偏壓效應。為了補償在替代電阻中，使用PMOS電晶體取代NMOS 電晶體所造成的電壓準位轉移，因此在我們提出的轉換器中建立一個電壓轉換的子電路。我們提出的轉換器對於大信號轉阻的線性度顯示出有重大的改善。電壓對電流轉換器的設計及製作是採用TSMC 0.35μm CMOS製程技術，製作的電路佔據面積267μm×197μm（~0.053mm2）採用3.3伏特的電源供應電壓，損耗功率低於3.92mW，在1伏特的峰對峰值輸入電壓下，輸出電流的總諧波失真(THD)低於1.5%。

An improved CMOS voltage-to-current converter is presented. PMOS transistors are employed in the resistor-replacement and voltage-level shifting of the proposed converter to avoid the body effect. To accurately annihilate the non-linear voltage terms, a better modeling of the drain-to-source current of the MOS transistor operating in the linear region is essential and is adopted. Specifically the substrate-bias effect of the MOS transistor is treated more thoroughly in our design. Consequently, the non-linearity of the large-signal transresistance of the converter, caused mainly by the body effect of a NMOS transistor in a previously published converter, is greatly minimized. In order to compensate the resultant voltage inversion created by the switching from NMOS transistors to PMOS transistors in the resistor-replacement and voltage-level shifting in the proposed circuit, a voltage-inversion sub-circuit is devised and employed in our converter. The voltage-to-current converter is designed and fabricated in a 0.35μm CMOS technology. The fabricated circuit occupies an area of 267μm×197μm（~0.053mm2） and dissipates less than 3.92mW from a 3.3 V supply. The measured and simulated data are in good agreement. For a 1 input voltage, the total harmonic distortion (THD) of the output current is less than 1.5%.

中文摘要 i
英文摘要 ii
第一章 緒論………………………………………………………………….. 1
1.1 研究背景……………………………………………………………. 1
1.2 研究目標……………………………………………………………. 2
1.3 論文架構……………………………………………………………. 3
第二章 運算放大器………………………………………………………… 4
2.1 基本架構……………………………………………………………. 5
2.1.1 伸縮組態運算放大器…………………………………………… 5
2.1.2 摺疊疊接運算放大器…………………………………………… 7
2.1.3 雙級運算放大器………………………………………………….. 8
2.1.4 增益增強電路……………………………………………………... 11
2.1.5 比較………………………………………………………………….. 12
2.2 放大器的特性規格………………………………………………. 13
2.2.1 直流增益……………………………………………………………. 13
2.2.2 輸入共模範圍……………………………………………………... 13
2.2.3 共模拒斥比………………………………………………………… 14
2.2.4 輸出電壓擺幅……………………………………………………... 14
2.2.5 輸入偏移電壓……………………………………………………... 15
2.2.6 單位增益頻寬……………………………………………………... 15
2.2.7 相位邊界……………………………………………………………. 16
2.2.8 電源拒斥比………………………………………………………… 17
2.2.9 迴轉率……………………………………………………………….. 17
2.2.10 穩定時間……………………………………………………………. 17
2.3 固定轉導偏壓電路………………………………………………. 18
第三章 能隙參考電壓產生電路………………………………………... 20
3.1 基本理論……………………………………………………………. 21
3.2 參考電壓基本型態………………………………………………. 26
3.3 能隙參考電路……………………………………………………... 27
3.3.1 與供應電源無關的偏壓………………………………………... 27
3.3.2 與溫度變化無關的偏壓………………………………………... 30
3.3.2.1 負溫度係數電壓………………………………………………….. 30
3.3.2.2 正溫度係數電壓………………………………………………….. 31
3.3.2.3 零溫度係數電壓參考電路…………………………………..... 32
3.3.3 PTAT電流產生器………………………………………………… 35
3.3.4 固定轉導偏壓……………………………………………………... 36
3.4 利用載子移動率與臨界電壓溫度效應互補特性的電壓產生電路…………………………………..………..................
37
3.4.1 零溫度係數工作點………………………………………………. 39
3.4.2 偏壓在零溫度係數工作點的穩定性………………………. 40
第四章 高線性CMOS電壓對電流轉換器………………………….. 43
4.1 電路架構……………………………………………………………. 44
4.2 提出的電壓對電流轉換器…………………………………….. 44
4.3 電晶體電流模型………………………………………………….. 47
第五章 高線性CMOS電壓對電流轉換器模擬、量測與佈局.. 49
5.1 摺疊曡接運算放大器之模擬............................................. 50
5.2 能隙參考電壓產生電路之模擬……………………………… 54
5.3 高線性CMOS電壓對電流轉換器之模擬與量測結果.. 56
5.4 高線性CMOS電壓對電流轉換器之佈局………………… 61
第六章 結論………………………………………………………………….. 64
參考文獻 65

[1] B. Razavi, Design of Analog Integrated Circuits, McGraw-Hill: Boston, 2001.
[2] D. A. Johns and K. W. Martin, Analog Integrated Circuit Design, John Wiley & Sons: New York, 1997.
[3] Phillip E. Allen and Douglas R. Holberg, CMOS Analog Circuit Design, Oxford University Press: New York, 2002.
[4] B.J. Hosticka, “Improvement of the Gain of CMOS Amplifiers, “IEEE J. of Solid-State Circuits, vol. 14, pp. 1111-1114, Dec. 1979.
[5] L.L.G. Vermaas, C.R.T.de Mori, R.L.Moreno,A. Pereira and Edgar Charry R. “A Bandgap Voltage Reference Reference Using Digital CMOS Process,”IEEE International Conference on Electronics, Circuits and Systems, Vol. 2 pp.303-306,1998.
[6] D. Hilbiber,”A New Semiconductor Voltage Standard,”ISSCC Dig. Of Tech. Papers,pp. 32-33,Feb. 1964.
[7] Filanovsky, I.M. Allam, A.;” Mutual Compensation of mobility and Threshold Voltage Temperature Effect with Applications in CMOS circuits ”, Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on [see also Circuits and Systems I: Regular Papers, IEEE Transactions on], Volume 48, Issue 7, July 2001 Page(s):876 – 884
[8] P. P. Vervoort and R. F. Wassenarr, “A CMOS rail-to-rail linear V-I converter,” in Proc. 1995 IEEE International Symposium on Circuits and Systems, pp. 825-828, April 1995.
[9] S. R. Zarabadi, M. Ismail, and C. Hung, “High performance analog VLSI computational circuits,” IEEE Journal of Solid-State Circuits, vol. 33, no. 4, pp.644-649, April 1998.
[10] B. Fotouhi, “All-MOS voltage-to-current converter,” IEEE Journal of Solid-State Circuits, vol. 36, no. 1, pp.147-151, January 2001.
[11] C. C. Hung, M. Ismail, K. Halonen, and V. Porra, “A low-voltage rail-to-rail CMOS V-I converter,” IEEE Transactions on Circuits and Systems-II, vol. 46, no.6, pp.816-820, June 1999.
[12] B. Palau, F.V. Santos, J. M. Karam, B. Courtois, and H. Musak, “New ISFET sensor interface circuits for biomedical applications,” Sensors and Actuators, B, 57, PP. 63-68, 1999.
[13] R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits for Signal Processing, New York: Wiley, 1986.
[14] B. J. Sheu, D. L. Scharfetter, P. Ko, and M. Jeng, “BSIM: Berkerly short-channel IGFET model for MOS transistors,” IEEE Journal of Solid-State Circuits, vol. 22, no. 4, pp. 558-566, August 1987.
[15] Filanovsky, I.M. Allam, A.;” Mutual Compensation of mobility and Threshold Voltage Temperature Effect with Applications in CMOS circuits ”, Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on [see also Circuits and Systems I: Regular Papers, IEEE Transactions on], Volume 48, Issue 7, July 2001 Page(s):876 – 884
[16] Buck, A.E.; McDonald, C.L.; Lewis, S.H.; Viswanathan, T.R.;” A CMOS bandgap reference without resistors ”, Solid-State Circuits, IEEE Journal of , Volume: 37 , Issue: 1 , Jan. 2002, Pages:81 – 83
[17] Dillard, W.C.;” A high-voltage temperature compensated logarithmic amplifier suitable for integration in a BiCMOS power controller IC”,Applied Power Electronics Conference and Exposition, 2004. APEC ''04. Nineteenth Annual IEEE , Volume: 1 , 22-26 Feb. 2004 ,Pages:258 - 263 Vol.1
[18] Lee, C.-H.; Park, H.-J.;” All-CMOS temperature independent current reference”, Electronics Letters , Volume: 32 , Issue: 14 , 4 July 1996,Pages:1280 - 1281.
[19] Bendali, A.; Savaria, Y.;” Low-voltage bandgap reference with temperature compensation based on a threshold voltage technique”, Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on , Volume: 3 , 26-29 May 2002, Pages:III-201 - III-204 vol.3
[20] Min, D.-S.; Cho, S.; Jun, D.S.; Lee, D.-J.; Seok, Y.; Chin, D.;” Temperature-compensation circuit techniques for high-density CMOS DRAMs”, Solid-State Circuits, IEEE Journal of , Volume: 27 , Issue: 4 , April 1992 ,Pages:626 – 631
[21] Wu, Y.; Chunlei Shi; Ismail, M.; Olsson, H.;” Temperature compensation design for a 2.4 GHz CMOS low noise amplifier”, Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on , Volume: 1 , 28-31 May 2000,Pages:323 - 326 vol.1
[22] Aldea, C.; Sabadell, J.; Celma, S.; Martinez, P.A.;” Optimized design for the high-swing cascode mirror”, Circuits and Systems, 1998. Proceedings. 1998 Midwest Symposium on 9-12 Aug. 1998 Page(s):233 – 236
[23] Coelho Vincence, V.; Galup-Montoro, C.; Cherem Schneider, M.;” A high-swing MOS cascode bias circuit”, Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on], Volume 47, Issue 11, Nov 2000 Page(s):1325 – 1328
[24] Vincence, V.C.; Montoro, C.G.; Schneider, M.C.;” A high-swing MOS cascode bias circuit for operation at any current level”, Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on Volume 5, 28-31 May 2000 Page(s):489 - 492 vol.5