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研究生:林文彥
研究生(外文):Wen-yan Lin
論文名稱:不同複晶矽閘極與氮化矽覆蓋層厚度之區域性應變N通道金氧半電晶體之可靠性研究
論文名稱(外文):Study of Reliability in the Local Strained n-channel MOSFET by Different Thickness of Poly-Si Gate and Nitride Capping Layer
指導教授:黃柏仁黃柏仁引用關係
指導教授(外文):Bohr-ran Huang
學位類別:碩士
校院名稱:國立雲林科技大學
系所名稱:電子與資訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:中文
論文頁數:106
中文關鍵詞:熱載子效應加壓後閘極漏電流可靠性金氧半電晶體區域性應變
外文關鍵詞:hot carrier effectreliabilityMOSFETSILCstrain
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在本篇論文中,區域性應變之nMOSFET,主要是利用氮化矽薄膜本身具有的高應力特性來控制元件通道中的應力大小,進而改善了載子遷移率。由於不同的氮化矽層厚度所造成的應力也不盡相同,所以在可靠性上的影響也會有所不同。而本論文則是著重在不同應力的nMOSFET在可靠性上的影響。
對於不同厚度的氮化矽,經過Hot Carrier Stress後,我們得到氮化矽250nm為最差,而沒有氮化矽覆蓋則為最好。此外,我們嘗試改變汲極電壓以及元件的操作溫度,探討這些變化對於元件穩定性造成何種的影響。我們還探討了加壓後所引起的閘極漏電流,比較其加壓前後漏電流的變化。
隨著製程技術不斷進步以及元件尺寸越縮越小的趨勢下,對於應用區域性應變技術來改善元件的操作速度,將備受矚目。
In this study, a local strained n-channel MOSFET has been fabricated by utilizing a heavy mechanical stress SiNx-capping layer, and further improves the carrier mobility to achieve the purpose of high operation speed. We investigate the local strained effects on nMOSFETs by different Poly-Si and nitride thicknesses. Therefore, the study focuses on the relation of reliability and strain.
After hot carrier stress, the devices with 250-nm SiNx show the largest ΔVth shift and transconductance degradation whereas 170-nm devices show better reliability. As we supply the different drain voltage or operation temperature, the reliability of devices will be change. SILC is an increase in gate oxide leakage current resulting from the application of a stress voltage or current. It is an important concern in scaling gate oxide thickness.
As the device dimension continues to scale down, the local strain technology in future CMOS application will be more respected.
中文摘要
英文摘要
誌謝
目錄
表目錄
圖目錄
第一章 緒論
1-1 背景
1-2 論文架構
第二章 元件製作及電性與可靠性量測方法
2-1 元件製作
2-2 基本電性量測
2-2-1 ID -VGS 特性曲線
2-2-2 ID-VDS 特性曲線
2-2-3 Charge Pumping
2-3 可靠性理論及量測方法
2-3-1 熱載子量測方法
2-3-2 Stress-Induced Leakage Current量測方法
第三章 結果與討論
3-1 元件基本特性
3-2 熱載子效應
3-2-1 時間對熱載子效應之影響
3-2-2 閘極電壓對熱載子效應之影響
3-2-3 溫度對熱載子效應之影響
3-3 SILC
第四章 總結
參考文獻
【1】Ryuji Ohba and Tomohisa Mizuno, “Nonstationary Electron/Hole Transport in Sub-0.1μm MOS Devices: Correlation with Mobility and Low-Power CMOS Application”, in IEEE Trans. Electron Devices, vol. 48, pp. 338-343, Feb. 2001.
【2】Mark S. Lundstrom, “On the Mobility Versus Drain Current Relation for a Nanoscale MOSFET”, in IEEE Electron Device Lett., vol. 22, pp. 293–295, Jun. 1994.
【3】Dimitri A. Antoniadis, “MOSFET Scalability Limits and “New Frontier” Devices”, in Symp. VLSI Tech. Dig., 2002, pp. 2–5.
【4】Q. Q. Lo, D. L. Kwong, “Reliability characteristics of metal-oxide -semiconductor capacitors with chemical vapor deposited Ta2O5 gate dielectrics”, in Appl. Phys. Lett. 62, pp.975, 1993.
【5】Mark I. Gardner, Sundar Gopalan, Jim Gutt, Jeff Peterson, Hong-Jyh Li, and Howard R. Huff, “EOT Scaling and Device Issue for High-k Gate Dielectrics”, IWGI 2003.
【6】Jack C. Lee, H. J. Cho, C. S. Kang, S. J. Rhee, Y. H. Kim, R. Choi, C. Y. Kang, C. H. Choi, M. Akbar, “High-K Dielectrics and MOSFET Characteristics”, in IEDM Tech. Dig., pp. 441-444, 2003.
【7】Wen-Jie Qi, Renee Nieh, Byoung Hun Lee, Laegu Kang, Yongjoo Jeon, Katsunori Onishi, Tat Ngai, Sanjay Banerjee and Jack C. Lee, “MOSCAP and MOSFET characteristics using ZrO2 gate dielectric deposition directly on Si”, in IEDM Tech. Dig., pp.145, 1999.
【8】K. Onishi, C. S. Kang, R. Choi, H.-J. Cho, S. Gopalan, R. Nieh, S. Krishnan, and J. C. Lee, “Improvement of surface carrier mobility of HfO2 MOSFETs by high-temperature forming gas annealing”, in IEEE Trans. Electron Devices, vol. 50, pp. 384–390, Feb. 2003.
【9】C.-H. Ge, “Process-Strained-Si (PSS) CMOS technology featuring 3–D strain engineering”, in IEDM Tech. Dig., pp. 73–76, 2003.
【10】J. L. Hoyt, H. M. Nayfeh, S. Eguchi, I. Aberg, G. Xia, T. Drake, E. A. Fitzgerald, and D. A. Antoniadis, “Strained silicon MOSFET technology”, in IEDM Tech. Dig., pp. 23–26, 2002.
【11】J. Welser, J.L. Hoyt, and J.F. Gibons, “NMOS and PMOS Transistors Fabricated in Strained Silicon/Relaxed Silicon-Germanium Structures”, in IEDM Tech. Dig., pp. 1000-1002, 1992.
【12】J. Welser, J.L. Hoyt, and J.F. Gibons, “Evidence of Real-Space Hot-Electron Transfer in High Mobility, Strained-Si Multilayer MOSFETs”, in IEDM Tech. Dig., pp. 545-548, 1993.
【13】S. Takagi, T. Mizuno, T. Tezuka, N. Sugiyama, T. Numata, K. Usuda, Y. Moriyama, S. Nakaharai, J. Koga, A. Tanabe, N. Hirashita and T. Maeda, “Channel Structure Design, Fabrication and Carrier Transport Properties of Strained-Si/SiGe-On-Insulator (Strained-SOI) MOSFETs”, in IEDM Tech. Dig., pp. 57-60, Feb. 2003.
【14】K. Rim, J. Welser, J.L. Hoyt, and J.F. Gibons, “Enhanced Hole Mobilities in Surface-channel Strained-Si p-MOSFETs”, in IEDM Tech. Dig., pp.517-520, 1995.
【15】Deepak K. Nayak, K. Goto, A.Yutani, J. Murota, and Yasuhiro Shiraki, “High-Mobility Strained-Si PMOSFETs”, in IEEE Trans. Electron Devices, Vol. 43, pp. 1709-1716, Oct. 1996.
【16】Tomohisa Mizuno, Naoharu Sugiyama, Atsushi Kurobe, and Shin-ichi Takagi, “Advanced SOI p-MOSFETs with Strained-Si Channel on SiGe-on-Insulator Substrate Fabricated by SIMOX Technology”, in IEEE Trans. Electron Devices, Vol. 48, pp. 1612-1618, Aug. 2001.
【17】K. Rim, K. Chan, L. Shi, D. Boyd and J. Ott, “Fabrication and mobility characteristics of ultra-thin strained-Si directly on insulator (SSDOI) MOSFETs”, in IEDM Tech. Dig., pp. 49–52., 2003.
【18】Jung-Suk Goo, Qi Xiang, Y. Takamura, F. Arasnia, E.N. Paton, P. Besser, J. Pan and Ming-Ren Lin “Band offset induced threshold variation in strained-Si nMOSFETs”, in IEEE Electron Device Lett., vol. 24, pp. 568–570, 2003.
【19】S. Ito et al., “Mechanical stress effect of etch-stop nitride and its impact on deep submicrometer transistor design”, in IEDM Tech. Dig., pp. 247–250, 2000.
【20】A. Shimizu, K. Hachimine, N. Ohki, H. Ohta, M. Koguchi, Y. Nonaka, H. Sato, F. Ootsuka, “Local mechanical-stress control (LMC): A new technique for CMOS-performance enhancement”, in IEDM Tech. Dig., pp. 433–436, 2001.
【21】F. Ootsuka, S. Wakahara, K. Ichinose, A. Honzawa, S. Wada, H. Sato, T. Ando,H. Ohta, K. Watanabe, and T. Onai, “A Highly Dense, High-Performance 130nm node CMOS Technology for Large Scale System-on-a-chip Applications”, in IEDM Tech. Dig., pp. 575-578, 2000.
【22】K. Ota, K. Sugihara, H. Sayama, T. Uchida, H. Oda, T. Eimori, H. Morimoto, and Y. Inoue, “Novel Locally Strained Channel Technique for High Performance 55nm CMOS”, in IEDM Tech. Dig., pp. 358-361, 2002.
【23】S. Pidin, T. Mori, R. Nakamura, T. Saiki, R. Tanabe, S. Satoh, M. Kase, K. Hashimoto, T. Sugii, “MOSFET Current Drive Optimization Using Silicon Nitride Capping Layer for 65-nm Technology Node”, in Symp. VLSI Tech. Dig., pp. 54-55, 2004.
【24】David Onsongo, David Q. Kelly, Sagnik Dey, Rick L. Wise, C. Rinn Cleavelin, and Sanjay K. Banerjee, “Improved Hot-Electron Reliability in Strained-Si nMOS”, in IEEE Trans. Electron Devices, Vol. 51, pp. 2193-2199, Dec. 2004.
【25】Paul E. Nicollian, Mark Rodder, Douglas T. Grider, Peijun Chen, Robert M. Wallace, Sunil V. Hattangady, “Low Voltage Stress-Induced-Leakage-Current in Ultrathin Gate Oxides” , in IRPS, pp. 400-404, 1999.
【26】D. J. DiMaria and E. Cartier, “Mechanism for Stress-Induced Leakage Currents in Thin Silicon Dioxide Films”, in J. Appl. Phys., Vol. 78, No. 6, pp.3883-3894, 15 Sep. 1995.
【27】S. I. Takagi, N. Yasuda, A. Toriumi, “Experimental Evidence of Inelastic Tunneling and New I-V Model for Stress-Induced Leakage Current”, in IEDM Tech. Dig., pp. 323-326, 1996.
【28】E. Rosenbaum, L. F. Register, “Mechanism of Stress-Induced Leakage Current in MOS Capacitors”, in IEEE Trans. Electron Devices, Vol. 44, No. 2, pp. 317-323,1997.
【29】Donald A. Neamen, “Semiconductor Physics & Devices”, 2nd ED, Chapter 10
【30】Chung, Steve S., et al., “A Novel and Direct Determination of the Interface Traps in sub-100nm CMOS Devices with Direct Tunneling Regime (12~16Å)Gate Oxide”, in Symp. VLSI Tech. Dig., pp. 74-75, 2002.
【31】G. Groeseneken, H.E. Maes, N. Beltran, and R.F. De Keersmaecker, “A reliable approach to charge-pumping measurements in MOS transistors”, in IEEE Trans. Electron Devices., Vol. 31, pp. 42-53, 1984.
【32】Chao-Chi Hong and Jenn-Gwo Hwu, “Stress Distribution on (100) Si Wafer Mapped by Novel I-V Analysis of MOS Tunneling Diodes”, in IEEE Electron Device Lett., Vol. 24, pp.408-410, 2003.
【33】Jiann-Liang Su, Chao-Chi Hong, Jenn-Gwo Hwu, “Enhanced thermally induced stress effect on an ultrathin gate oxide”, in J. Appl. Phys., Vol. 91, pp.5423-5428, 2002.
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