臺灣博碩士論文加值系統

本論文主要是在探討積分三角調變器積分器飽和現象，因為高階的積分三角調變器訊號經過積分器的累加，容易照成積分器產生飽和現象，尤其這現象在硬體實現時更為明顯，無法將正確的數值傳遞給下一級的積分器，將會導致A/D轉換器產生錯誤的數值。於是我們針對此問題提出滑動模式控制來改善積分器飽和現象。經過模擬驗證，能有效的抑制積分器的輸出，避免積分器飽和的現象發生。大幅提升積分三角調變器A/D轉換器的整體效能。
以單一回授積分三角調變器為例加入控制器前系統的解析度為12bit，加入線性滑動面的控制器後解析度提升為22bit，加入非線性滑動面的控制器解析提升為18bit。MASH架構加入控制器前系統的解析度為12bit，加入線性滑動面的控制器後解析度提升為21bit，加入非線性滑動面的控制器解析提升為20bit。
積分三角調變器加入控制器之後，不僅成功的抑制積分器的輸出，使積分器不會發生飽和現象，也大幅提升系統的解析度。

The main purpose of this thesis is to deal with the saturation problem arisen from the integrator wind up in the loop of the delta-sigma modulators. The unwanted winding up effect is prominent especially in a high-order delta-sigma modulator. The effect will result in incorrect data at the integrator output which will propagate to the next stage and so on leading to incorrect result of the converter. We proposed a new anti- windup scheme by means of sliding mode control to tackle the saturation problem. After extensive simulation, we found that the anti-windup feedback control scheme can significantly improve the performance of a delta-sigma modulator.
Specifically, for a single integrator feedback delta-sigma modulator, by applying an anti-windup compensator at the feedback path, a 22-bit resolution converter can be obtained for a linear sliding manifold design and a 18-bit resolution converter for a nonlinear sliding manifold design. By contrast, we can only reach 12-bit resolution if the feedback compensator is not employed. In addition, we have shown that for a delta-sigma modulator with MASH structure, 21-bit and 20-bit resolutions when a linear sliding surface and nonlinear sliding surface, respectively, are used in the design of the feedback compensation scheme.
We reach a conclusion that a delta-sigma modulator with proposed feedback anti-windup compensator at each integrator feedback path may significantly improve the accuracy as well as the resolution of the converter.

中文摘要……………………...…..................................................................................i
英文摘要……………………...………………………...………………………...…...ii
誌謝……………………...………………………...………………………...………..iii
目錄……………………...………………………...………………………...………..iv
表目錄………………………………………………………………………………..vii
圖目錄…………………………………………………………………………….....viii
第一章 緒論…………………………………………………………………………..1
1.1研究動機 1
1.2研究目的 2
1.3章節概要 2
第二章 積分三角調變器基本原理與架構…………………………………………..4
2.1奈奎氏與超取樣A/D轉換器 4
2.1.1奈奎氏A/D轉換器 4
2.1.2超取樣A/D轉換器 4
2.2奈奎氏取樣率與量化誤差 6
2.2.1奈奎氏取樣率 6
2.2.2量化誤差 7
2.2.3超取樣技術 9
2.2.4雜訊移頻 11
2.3 積分三角調變器 12
2.3.1抗交聯濾波器 13
2.3.2一階積分三角調變器 15
2.3.3二階積分三角調變器 18
2.3.4高階積分三角調變器 20
2.4結論 23
第三章 可變結構控制………………………………………………………………25
3.1有限時間控制 25
3.2滑動模式簡介 26
3.3可變結構控制原理 27
3.3.1可變結構控制 27
3.3.2順滑模式控制 28
3.3.2.1迫近條件 29
3.3.2.2滑動條件 30
3.3.2.3滑動平面規劃 32
3.3.2.4等效控制 33
3.3.3滑動模式控制器設計 34
3.4應用可變結構控制器抑制積分三角調變器積分器飽和現象 35
3.4.1 線性滑動面 35
3.4.1.1滑動平面的設計 35
3.4.1.2迫近條件 36
3.4.1.3等效控制 37
3.4.2非線性滑動面 37
3.4.2.1滑動平面的設計 37
3.4.2.2迫近條件 38
3.4.2.3等效控制 39
3.5結論 39
第四章 積分三角調變器電路實現與模擬…………………………………………40
4.1積分三角調變器電路基本架構 40
4.1.1積分電路 40
4.1.2切換式電容積分器 42
4.2以切換式電容積分器實現積分三角調變器 45
4.2.1 一階積分三角調變器 45
4.2.2 二階積分三角調變器 45
4.3 Pspice 模擬與硬體電路實現 46
4.3.1 Pspice 模擬 46
4.3.1.1單一回授一階積分三角調變器 46
4.3.1.2單一回授二階積分三角調變器 48
4.3.2硬體電路實現 49
4.3.2.1單一回授一階積分三角調變器 49
4.3.2.2單一回授二階積分三角調變器 50
第五章 理論模擬結果與分析 52
5.1線性滑動面 52
5.1.1單一迴路二階積分三角調變器 52
5.1.1.1積分器輸出響應圖 52
5.1.1.2總斜坡失真因數（Total Harmonic Distortion；THD） 53
5.1.1.3加入控制器後，輸入與LPF輸出誤差響應圖 54
5.1.1.4頻譜分析 55
5.1.2 MASH架構：二階串級一階積分三角調變器 56
5.1.2.1積分器輸出響應圖 56
5.1.2.2總斜坡失真因數（Total Harmonic Distortion；THD） 57
5.1.2.3加入控制器後，輸入與LPF輸出的誤差響應圖 58
5.1.2.4頻譜分析 59
5.2非線性滑動面 60
5.2.1單一迴路二階積分三角調變器 60
5.2.1.1積分器輸出響應圖 60
5.2.1.2總斜坡失真因數（Total Harmonic Distortion；THD） 61
5.2.1.3加入控制器後，輸入與LPF輸出的誤差響應圖 61
5.2.1.4頻譜分析 62
5.2.2 MASH架構：二階串級一階積分三角調變器 63
5.2.2.1積分器輸出響應圖 63
5.2.2.2總斜坡失真因數（Total Harmonic Distortion；THD） 65
5.2.2.3加入控制器後，輸入與LPF輸出的誤差響應圖 65
5.2.2.4頻譜分析 66
第六章 結論與未來展望 70
6.1結論 70
6.2未來研究方向 71
參考文獻……………………………………………...……………………………...72

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