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研究生:楊佳勳
研究生(外文):Jia-Xun Yang
論文名稱:調整導線寬度大小來從事延遲與良率最佳化
論文名稱(外文):Wire Width Sizing for Delay and Yield Optimization
指導教授:林榮彬林榮彬引用關係
指導教授(外文):Rung-Bin Lin
學位類別:碩士
校院名稱:元智大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:英文
論文頁數:24
中文關鍵詞:最佳導線寬度最佳導線寬度最佳導線寬度
外文關鍵詞:optimal widthoptimal widthoptimal width
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在本論文中,兩個關於導線寬度的問題被研究。第一個問題是"在製程技術下最小導線間距下的最小導線寬度是否可以滿足以時間效能的觀點?"第二個問題是"當導線寬度在最佳導線寬度週遭變化時是延遲是否敏感?"我們發現的第一個問題答案"是",而對第二個問題的答案"否"。基於更後面的特性,導線寬度/間距可能被調整大小藉以降低內部導線的短路或開路以便增加生產良率並不會妨礙太多性能。
In this paper, two issues about wire width are investigated. The first one is that “Is the minimum wire width under the minimum wire pitch for a process technology good enough from the perspective of timing performance?” The second is that “Is delay sensitive to wire width variation around the optimal width?” We find that the answer to the first issue is “yes”, whereas the answer to the second is “not quite”. Based on the later property, wire width/spacing can be sized to reduce shorts or opens on interconnects so that manufacturing yield can be improved without hampering too much performance.
Table of Contents i
List of Figures ii
Symbol Definitions iii
Chapter 1. Introduction 1
1.1 Motivation 1
1.2 Scope of the Work 2
1.3 Thesis Organization 2
Chapter 2. Finding Optimal Wire Width 4
Chapter 3. Worst Case Delay Measurement 7
Chapter 4. Experimental Results 9
Chapter 5. Applications of Analysis Results 20
Chapter 6. Conclusion 22
References 23
[1]J. Cong, K. S. Leung and D. Zhou, “Performance-driven interconnect design based on distributed RC delay model,” in Proc. Design Automation Conf., June 1993, pp.606–611.
[2]J. Cong and K. S. Leung, “Optimal wire sizing under the distributed Elmore delay model,” in Proc. Int. Conf. Computer Aided Design, Nov. 1993, pp.634–639.
[3]J. Cong and L. He, “Optimal wire sizing for interconnects with multiple sources,” ACM Trans. Design Automation Electron. Syst., vol. 1, no. 4, Oct. 1996, pp.478–511.
[4]S. S. Sapatnekar, “RC interconnect optimization under the Elmore delay model,” in Proc. Design Automation Conf., June 1994, pp.387–391.
[5]J. P. Fishburn and C. A. Schevon, “Shaping a distributed-RC line to minimize Elmore delay,” IEEE Trans. Circuits Syst. I: Fund. Theory Applicat., vol. 42, no. 12, Dec. 1995, pp.1020–1022.
[6]C. P. Chen, Y. P. Chen and D. F. Wong, “Optimal wire-sizing formula under the Elmore delay model,” in Proc. Design Automation Conf., June 1996, pp.487–490.
[7]C.-P. Chen and D. F.Wong, “Optimal wire sizing function with fringing capacitance consideration,” in Proc. Design Automation Conf., June 1997, pp.604–607.
[8]J. P. Fishburn, “Shaping a VLSI wire to minimize Elmore delay,” in Proc. European Design and Test Conf., Mar. 1997, pp.244 – 251.
[9]Y. Gao and D. F.Wong, “Optimal shape function for a bi-directional wire under Elmore delay model,” in Proc. Int. Conf. Computer Aided Design, Nov. 1997, pp.622–627.
[10]J. Cong and Z. Pan, “Wire width planning for interconnect performance optimization,” IEEE Transactions on Computer-aided Design, volume 21, 2002, pp.319-329.
[11]C.J. Alpert, A. Devgan, J. P. Fishburn and S. T. Quay, "Interconnect synthesis without wire tapering," IEEE Transactions on Computer-Aided Design, January, 2001, pp.90-104.
[12]S.C. Wong, G.Y. Lee and D.J. Ma, “Modeling of interconnect capacitance, delay, and crosstalk in VLSI,” IEEE Transactions on Semiconductor Manufacturing, volume 13, 2000, pp.108-111.
[13]Richard Brent, Algorithms for minimization without derivatives, Prentice-Hall (1973).
[14]http://www.gnu.org/software/gsl.
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