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研究生:邱義文
研究生(外文):Yi-Wen Chiu
論文名稱:聲學迴音消除器之研究:雙邊談話機制及降低偏差之非線性迴授濾波器
論文名稱(外文):A study of acoustic echo cancellation : double talk detection and bias removal nonlinear feedback filter
指導教授:李仲溪
指導教授(外文):Junghsi Lee
學位類別:碩士
校院名稱:元智大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:中文
論文頁數:72
中文關鍵詞:聲學迴音消除器雙邊談話機制適應性無限脈衝響應濾波器FPGA實現
外文關鍵詞:Acoustic Echo CancellationDouble-talk detection(DTD)Adaptive IIR filterField Programmable gate array (FPGA) Implementation
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本論文主要研究聲學迴音消除器中的雙邊談話機制、方程式誤差適應性無限脈衝響應濾波器的改良以及在FPGA上實現定點數適應性濾波器。
我們提出的雙邊談話機制包含遠端語音偵測、近端語音偵測和輔助濾波器三種架構。此機制能有效分辨迴音與近端語音,使適應性濾波器達到消除迴音而不破壞近端語音的好處。本論文也提出一個多歩階增益回授項係數正規化方程式誤差線性濾波器。我們將此想法推廣至非線性適應性濾波器,完成具有多歩階增益的降低偏差之非線性迴授濾波器。此演算法相較於一般方程式誤差適應性濾波器具有快速收斂與消除估測偏差的優點。另外,我們使用硬體描述語言Verilog HDL在FPGA上實現具管線化定點數適應性濾波器,並應用於聲學迴音消除上。
The main purpose of this thesis is about double talk detector and bias removal nonlinear feedback filter in acoustic echo cancellation. We also use field programmable gate array to implement fixed-point adaptive filter.
The proposed Double talk detector includes an auxiliary filter, a far-end speech detector and a near-end speech detector and differentiates between echo and near-end speech efficiently. This thesis also presents a multistep size monic normalization equation-error linear filter. We extend the idea to a nonlinear adaptive filter and derive a multistep size bias removal nonlinear feedback filter. The algorithms enjoy fast convergence behavior and can remove biased estimates associated with conventional equation-error adaptive filter. Besides, we use FPGA to implement a pipelined fixed-point adaptive filter with application in acoustic echo cancellation.
中文摘要
英文摘要
誌謝
目錄
圖目錄
表目錄
第一章 序論
1.1研究背景
1.2 論文動機
1.3 論文組織
第二章 具有雙邊談話機制之聲學迴音消除器
2.1 簡介
2.2 迴音消除演算法
2.3 雙邊談話偵測機制
2.3.1 Park提出之雙邊談話偵測機制
2.3.2 輔助濾波器架構
2.3.3 遠端語音偵測機制
2.3.4 近端語音偵測機制
2.3.5 聲學迴音消除器控制策略
2.4 聲學迴音消除之模擬
2.4.1 實驗一:交越相關係數門檻值設定
2.4.2 實驗二:雙邊談話機制之驗證(1)
2.4.3 實驗三:雙邊談話機制之驗證(2)
2.5 結論
第三章 多歩階增益之降低偏差適應性演算法
3.1 簡介
3.2 多步階增益迴授項係數正規化方程式誤差線性濾波器
3.3 降低偏差之非線性迴授濾波器
3.4 實驗結果
3.4.1 實驗一:MSS-MNEE於線性系統(1)
3.4.2 實驗二:MSS-MNEE於線性系統(2)
3.4.3 實驗三:MSS-MNEEBF於雙線性系統
3.5 結論
第四章 FPGA上實現定點數適應性濾波器
4.1 簡介
4.2 具管線化之適應性濾波器
4.2.1 具延遲性之最小平均平方演算法
4.2.2 具管線化之適應性直接形式濾波器
4.2.3 具管線化之適應性移項形式濾波器
4.3 定點數適應性濾波器電路架構
4.3.1 乘法器簡化:SPT量化法
4.3.2 基本電路架構
4.3.3 具管線化之適應性直接形式濾波器電路架構
4.3.4 具管線化之適應性移項形式濾波器電路架構
4.4 實驗結果
4.4.1 8階定點數適應性濾波器實驗
4.4.2 128階具管線化之適應性直接形式濾波器實驗
4.4.3 128階具管線化之適應性移項形式濾波器實驗
4.5 結論
第五章 結論
5.1 論文總結
5.2 未來工作
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