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研究生:郭年益
研究生(外文):Kuo, Nien I
論文名稱:以TIC6xDSP晶片實現可重組數位傳收機
論文名稱(外文):Implementation of a reconfigurable digital transceiver using the TI C6x DSP
指導教授:蘇英俊
指導教授(外文):Su, Ing Jiunn
學位類別:碩士
校院名稱:國防大學中正理工學院
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:中文
論文頁數:68
中文關鍵詞:軟體定義無線電傳收機可重組性
外文關鍵詞:Software Defined Radio (SDR)ReconfigurableTransceiver
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軟體定義無線電(Software Define Radio)理論的出現,被視為解決新一代通訊,支援多重標準、多模式操作及功能可重組(Reconfigurable)需求的一項重要技術,這項技術可以在一個可程式的無線電硬體上,利用可重組的軟體技術來達到支援多個通訊頻段、調變方式及不同頻寬需求的操作,增加了硬體使用的彈性。
本論文利用數位信號處理晶片易於程式化的優點,研究以TI C6x晶片的發展工具做為無線電的核心運算平台,搭配自行設計的連接子卡,將數位類比轉換器及類比數位轉換器整合成一個可重組的傳收機系統實體。在軟體演算法方面,這裡使用C語言發展了QPSK及16QAM兩種調變方式來測試傳收機的功能,經由演算法的計算錯綜性分析及實驗驗證結果,本傳收機傳輸符碼率可以輕易達到750K symbols/sec的效能。
The philosophy of Software Defined Radio being a key technology for next generation wireless communications, needed to support multi-standard, multi-mode and function re-configurable radio designs. This technology refers to the class of reconfigurable radios in which hardware is reprogrammed to support different frequencies, frequency bandwidths as well as different modulation schemes resulting in significant increases in hardware flexibility.
This thesis exploits easy to use DSP programming software to reconfigure a transceiver built around the TI C6x DSK and ADC/DAC connected through an experimental daughter card specifically designed for this purpose.
Two different modulation schemes (QPSK and 16QAM) are implemented using C algorithm to demonstrate the computational complexity of the proposed system. Supporting experiments presented in this thesis shows attainable symbol rate is 750K symbols/sec.
誌謝 ii
摘要 iii
ABSTRACT iv
目錄 v
表目錄 vii
圖目錄 viii
符號說明 x
縮寫表 xii
1. 緒論 1
1.1 軟體無線電概念 1
1.2 研究動機 2
1.3 論文架構 3
2. 背景介紹 4
2.1 可重組傳收機架構 4
2.2 傳收機硬體簡介 5
2.2.1數位信號處理器發展工具 5
2.2.2 數位類比轉換器 6
2.2.3 類比數位轉換器 6
2.2.4 射頻前端 8
2.3 基頻訊號處理 9
2.3.1 調變型態 9
2.3.2 星圖點對映及差分編碼 12
2.3.3 基頻調變 15
2.3.4 波型整型濾波器 17
2.3.5 自動增益控制 18
2.3.6 亂碼器及解亂碼器 19
2.3.7 時序回復 20
3. 傳收機硬體整合 24
3.1 發射機架構 24
3.2 接收機架構 25
3.3 自製子卡之設計 25
3.3.1 FIFO介面 25
3.3.2 子卡介面規範 27
3.3.3 時序限制 30
3.3.4 電路模擬與佈線 33
4. 傳收機軟體實現 43
4.1 亂碼器及解亂碼器實現 43
4.2 差分編碼及星圖點對映之實現 44
4.3 波型整型濾波器實現 46
4.4 自動增益控制的實現 48
4.5 時序回復的實現 49
5. 效能及結果 53
5.1 傳收機測試設置 53
5.2 計算效能 53
5.3 測試結果 55
6. 結論及建議 57
參考文獻 58
附錄壹 61
自傳 68
[1] Tuttlebee, W., Software Defined Radio: Enabling Technologies, John Wiley & Sons Ltd, England, pp. 5-15, 2002.
[2] Buracchini, E., “The Software Radio Concept,” IEEE Communications Magazine, pp. 138-143, September, 2002.
[3] Finger, R., “Using TI FIFOs to Interface High-Speed Data Converters With TI TMS320 DSPs,” Texas Instruments, Dallas, Texas, Application Report SDMA003, June, 2001.
[4] “TMS320C6416T DSK Technical Reference,” Rev. A, Spectrum Digital Inc., Stafford, November, 2004.
[5] “AD9777 Data Sheets,” Rev. B, Analog Devices Inc., U.S.A., 2004.
[6] “AD9248 Data Sheets,” Rev. A, Analog Devices Inc., U.S.A., 2005.
[7] “AD8349 Data Sheets,” Rev. A, Analog Devices Inc., U.S.A., 2004.
[8] “AD8347 Data Sheets,” Rev. 0, Analog Devices Inc., U.S.A., 2001.
[9] Proakis, J. G. and Salehi, M., Communication Systems Engineering 2nd Edition, Prentice Hall Inc., New Jersey, pp. 354-359, 2002.
[10] Tretter, S. A., Communication System Design Using DSP Algorithms With Laboratory Experiments For The TMS320C6701 And TMS320C6711, Kluwer Academic/Plenum Publishers, New York, pp. 188-219, 2003.
[11] “A Technical Tutorial On Digital Signal Synthesis,” Analog Device Inc., U. S. A., 1999.
[12] Gardner, F. M., “Interpolation in Digital Modems-Part I: Fundamentals,” IEEE Transactions on Communications, Vol. 41, pp. 501-507, March, 1993.
[13] Meyr, H., Moeneclaey, M. and Fechtel, S. A., Digital Communication Receivers, John Wiley & Sons Inc., U. S. A., pp. 523-530, 1998.
[14] Erup, L., Gardner, F. M. and Harris, R. A., “Interpolation in Digital Modems-Part II: Implementation And Performance,” IEEE Transactions on Communications, Vol. 41, pp. 998-1008, June, 1993.
[15] “SN74V225, 1024×18, DSP-SYNC First-In, First-Out Memories,” Datasheet SCAS636E, Texas Instruments, Dallas, Texas, April, 2000.
[16] Castille, K., “TMS320C6000 EMIF to External FIFO Interface,” Texas Instruments, Dallas, Texas, Application Report SPRA543, May, 1999.
[17] Bell, D., “TMS320 Cross-Platform Daughtercard Specification Revision 1.0,” Texas Instruments, Dallas, Texas, Application Report SPRA711, November, 2000.
[18] “TMS320C6414T, TMS320C6415T, TMS320C6416T Fixed-Point Digital Signal Processors,” Texas Instruments, Dallas, Texas, Datasheet SPRS226H, November, 2003.
[19] “TMS320C6000 Peripherals Reference Guide,” Texas Instruments, Dallas, Texas, Technical Documents SPRU190D, February, 2001.
[20] “TMS320C6000 EVM Daughterboard Interface,” Texas Instruments, Dallas, Texas, Application Report SPRA478, December, 1998.
[21] “High-Speed DSP Systems Design,” Texas Instruments, Dallas, Texas, Reference Guide SPRU889, May, 2005.
[22] Brooks, D. “PCB Impedance Control,” http://ultracad.com/articles.htm。
[23] Katz, L. “Bus-Interface Devices with Output-Damping Resistors or Reduced-Drive Outputs,” Texas Instruments, Dallas, Texas, Application Report SCBA012A, August, 1997.
[24] Brooks, D. “Crosstalk Coupling: Single-Ended vs. Differential,” Technical Publication, http://www.mentor.com/。
[25] Oppenheim, A. V., Schafer, R. W. and Buck, J. R., Discrete-Time Signal Processing 2nd Edition, Prantice Hall Inc., New Jersey, pp. 410-411, 1999.
[26] Gardner, F. M., “A BPSK/QPSK Timing-Error Detector for Sampled Receivers,” IEEE Transactions on Communications, Vol. Com-34, pp. 423-429, May, 1986.
[27] Johnson, C. R. and Sethares, W. A., Telecommunication Breakdown Concepts of Communication Transmitted via Software-Defined Radio, Pearson Prentice Hall, New Jersey, pp. 379-380, 2004.
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