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研究生:李軒宇
研究生(外文):Hsuan-Yu Lee
論文名稱:壓電振動式低應力拋光研磨系統之研發
論文名稱(外文):Development of the Piezoelectric based Vibration Polishing System for Low Stress CMP
指導教授:蔡孟勳蔡孟勳引用關係鄭友仁
指導教授(外文):Meng-Shiun TsaiYeau-Ren Jeng
學位類別:碩士
校院名稱:國立中正大學
系所名稱:機械工程所
學門:工程學門
學類:機械工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:94
語文別:英文
論文頁數:52
中文關鍵詞:化學機械研磨振動低應力
外文關鍵詞:CMPvibrationlow stress
相關次數:
  • 被引用被引用:1
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  • 下載下載:107
  • 收藏至我的研究室書目清單書目收藏:0
隨著半導體元件線體製程要求大容積化及高解析度的情況下,導體連線架構中電阻及電容所產生的寄生效應,成為電路訊號傳輸速度受限的主要原因之一。半導體內部連線結構中低介電常數材料與銅導線的整合可應用於解決此問題。然而,低介電常數材料無法承受高應力,因此在半導體表面加工中,低應力化學機械研磨製程成為一項重要的製程。本論文提出一嶄新的概念,在機械化學研磨製程中利用壓電致動器施加動態壓力。將此與傳統機械化學研磨製程做比較,此方式的目的希望在保護晶圓內部低介電常數材料層的前提下產生較高的晶圓表面材料移除率。我們以磨耗模式的力平衡為基礎建立一材料移除率理論模式,用以瞭解研磨顆粒與晶圓表面於彈性、彈塑性及彈性之接觸行為,如此可計算晶圓表面材料移除率。除此,模擬參數分析用以瞭解各實驗變數之交互關係,而實驗數據用以驗證設計概念及與理論值做比較。最後,可發現由數值模擬結果中所觀察到的現象與實驗數據大致吻合。
As the demand of the integrated circuit process requires more capacity and higher resolution, interconnect resistance-capacitance (RC) time delay becomes an important factors. A material with the low dielectric constant (low-K) and copper wire can be utilized to achieve low RC time constant. However, the low K material cannot sustain high stress, and thus low-stress chemical mechanical polishing (CMP) process becomes an important process for surface manufacturing of semiconductor. This thesis proposes a novel concept that uses piezoelectric actuators to provide a dynamic pressure for the CMP process. As compared to the traditional CMP process, the objects of this approach are to achieve higher material removal rate (MRR) and also protect the inner layer of the low K material in the wafer. Based on the force balance of the wear model, theoretical MRR models are developed to investigate the elastic, elastic-plastic, and plastic contact behavior over abrasive and wafer surface interface such that the MRR can be estimated. The parameter study is performed to understand the correlation between designed variables. Experiments are conducted to verify the concept and to compare with the simulation result. The phenomenon that observed in the simulation is also demonstrated in the experiments.
CHAPTER 1. INTRODUCTION 1
1-1. Motivation and Objective 3
1-2. Literature Review 3
1-3. Architecture of Thesis 5
CHAPTER 2. EXPERIMENTAL DESCRIPTION OF LOW STRESS POLISHING PROCESSING 7
2-1. Force Generation 8
2-2. Concept of the Proposed Design 8
2-3. Experimental Setup 9
CHAPTER 3. MODELING OF LOW STRESS MATERIAL REMOVAL MECHANISM IN CHEMICAL MECHANICAL POLISHING 14
3-1. Introduction to Modeling for CMP 14
3-2. Real Area of Contact Over Pad-Wafer Interface 15
3-3. Number of Abrasives Participating in Wafer Material Removal 17
3-4. Construction of Contact System 18
3-4.1 Behavior of Indentation 18
3-4.2 Abrasive indentation depth into wafer and pad surface 19
3-4.3 Force equilibrium over wafer/abrasive/pad interface 21
3-5. Determination of Material Removal Rate 23
CHAPTER 4. SIMULATION AND EXPERIMENTAL RESULTS FOR LOW STRESS POLISHING 29
4-1. Polishing Model Validation and Comparison with Experiment Results 29
4-1.1 MRR model with static applied pressure 29
4-1.2 MRR model with applying dynamic force 30
4-2. Parameter Study 31
4-2.1 The variation of wafer hardness 31
4-2.2 The variation of slurry concentration 31
4-2.3 The variation of pad asperity height 32
4-2.4 The variation of abrasive diameter 32
CHAPTER 5. CONCLUSIONS AND FUTURE WORK 47
5-1. Conclusions 47
5-2. Future Work 47
REFERENCE 49
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[34]http://www.piezomechanik.com/
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