臺灣博碩士論文加值系統

這篇論文提出一個同步多緒精簡指令集處理器搭配非阻礙式load/store。 釵h應用存在著多工的特性，例如在視訊和音訊編解碼中的平行資料運算。但是傳統的精簡指令集處理器並不能利用這個天生固有的平行度。相反的，多緒技術能讓多於一個指令流在處理器中存在並運算。它共享硬體資源並隱藏記憶體延遲的能力提升了效能和效率。
然而,雖然多執行緒處理器在多處理上表現的很好，他在指令的發出頻寬和產能上有著限制。在這份論文中，我們設計了一個4way 2issue的同步多緒精簡指令集處理器來改進上述的缺點，而其中的設計複雜度不高且面積的增多不大。此外我們提供了非阻礙式的load/store隱藏記憶體延遲。最後，這個同步多緒精簡指令集處理器的時脈能達到210MHz。

This paper proposes a simultaneous multithreading RISC processor with non-blocking load/store.
Many applications exhibit multi-tasking characteristics, such as parallel data operations in video and audio codec. But traditional RISC processor can not take advantage of this inherent parallelism. Instead, multithreading technique enables more than one instruction string
to be active in the CPU. Its ability to share hardware resource and hide memory latency would improve performance and efficiency. While multithreading processor is good at multi-processing, it has the limit on issuebandwidth
and throughput. In this thesis, we design a 4-way, 2-issue SMT RISC processor to improve that with low design complexity and low area increment incurred. Besides, we
also provide non-blocking load/store to hide memory latency. Finally, the clock rate of SMT RISC processor can reach of 210MHz.

1 Introduction
1.1 Motivation
1.2 Unicore-VisoMT architecture
1.3 Simultaneous Multithreading Helper RISC
1.4 Thesis Organization
2 Background and Related Work
2.1 From ILP to TLP
2.2 Hardware multithreading
2.3 Multithreading RISC processors of nowadays
2.4 Summary
3 UniCore-VisoMT
3.1 Overview
3.2 Helper RISC under UniCore-VisoMT
3.2.1 Control and support the program flows of simultaneous multiple threads
3.2.2 Unify the load/store interface of VisoMT (cluster2)
3.2.3 Fast data register file switch
4 SMT Helper RISC
4.1 Simultaneous Multithreading Architecture
4.2 Instruction Set
4.3 Architecture Design
4.3.1 Front-end
4.3.2 Dynamic Scheduling
4.3.3 Micro-architecture design of Helper RISC
4.3.4 Non-blocking Load/store
5 Performance Evaluation
5.1 Hardware Synthesis
5.2 Simulation result
6 Conclusion

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