臺灣博碩士論文加值系統

為達到低成本/低必v的高效能設計目標與多重弁?可擴充性的設計彈性，本論文提出一包含三項新技術之可擴充性資料路徑為基礎之設計方法(A Programmable Data-path (PD)-based Design Approach)，可設計具有多重弁鉬P可擴充性的多媒體視訊編碼硬體架構，並以轉換編碼為例闡明所提技術的正確性與實用性。本論文所提之設計技術從演算法推導、硬體架構設計、邏輯及電路設計等層面進行最佳化設計考量，以達到低成本/低必v的設計目標。所提之三項新設計技術包含：以可程式資料路徑(Programmable data-path)為基礎的架構設計技術、分散式算術演算法(Adder-based DA) 設計技術與虛必v消除設計技術(SPST)。利用這些技術，本論文提出了三項設計實例，分別為：通曉性能之轉換編碼設計（設計一）、通曉能量的SA-DCT/IDCT設計（設計二）與高效能之H.264 Direct 2-D轉換編碼設計（設計三）。設計一擁有計算DCT/IDCT與H.264整係數轉換編碼之多重弁遄A同時可依據應用需求而調整適合硬體成本的通曉性能可擴充性。與設計一相比，設計二增加計算SA-DCT/IDCT之弁鉬P通曉能量之彈性。設計三則可完成H.264之二維整係數轉換編碼而不須使用轉置記憶體，以節省硬體成本。此外，虛必v消除設計技術可消除電路中非必要的動態必v消耗，本論文將此技術應用到設計三並實作成晶片，成它a證明所提設計技術之正確性與實用性。利用這些技術所設計的轉換編碼電路比傳統以乘法器為基礎或處理器為基礎之轉換編碼電路擁有更高的計算效率。除了上述本論文中所探討的三種設計實例之外，本論文所提出的可擴充性之架構設計方法與分散式算術演算法亦適用於其它的轉換編碼如傅立葉轉換、濾波器和量化器等電路，虛必v消除設計技術則可應用於各式多媒體視訊應用所需的數位電路如移動補償器、移動估測器和乘加器等以達到有效節省必v消耗的目的。

For high-efficiency video coding, this dissertation proposes a programmable data-path (PD)-based design approach which includes three new techniques to design the VLSI architecture that owns both the versatility and scalability. Meanwhile, this dissertation explains the correctness and practicability of the proposed design approach based on the example of transform coding design. The proposed design techniques which includes the Programmable Data-path (PD) based architectural design technique, adder-based DA formulation, and Spurious Power Suppression Technique (SPST) provide optimization in the view points of algorithmic, architectural, logic, and circuit levels to achieve low-cost and low-power design goals. Using those techniques, this dissertation proposes three design examples which are (1) a performance-aware DCT/IDCT design, (2) an energy-aware SA-DCT/IDCT design, and (3) a high-performance direct 2-D transform coding design. The design (1) can perform multi-function of computing the block-based DCT/IDC and integer transforms for H.264. Besides, it possesses the performance-aware scalability of configuring appropriate hardware for different performance requirements on demand without requiring additional I/O data registers. The design (2) can compute SA-DCT/IDCT in addition, and possesses the energy-aware feature that allows the trade-off of lower energy consumption with less demand of data precision. The design (3) can efficiently compute 2-D transforms without using a transpose memory, which saves much area cost. Moreover, SPST can suppress the spurious dynamic power dissipation which exists in the data-paths for multimedia VLSI designs. This technique has been applied on the design (3) and the combined design has been physically implemented as a chip. The success of this chip implementation proves the correctness and practicability of the proposed design techniques. In addition to applying to the three design examples presented in this dissertation, the proposed design technique can also be adopted in designing FFT, filters, quantizers, motion compensators, motion estimators, and multiply-accumulators.

Abstract (Chinese)……………………………………………..i
Abstract (English)…………………………………………….iii
Acknowledgement……………………………………………..v
Contents………………………………………………………vii
Figure Captions…………………………………………….. ..xi
Table Captions……………………………………………..... xv

Chapter 1 Introduction……………………………………….1
1.1 Evolution of Video Coding Systems…………………………1
1.2 Design Challenges of Realizing Video Coding Systems…….3
1.3 Motivation…………………………………………………....7
1.4 Organization of this Dissertation…………………….……...11
Chapter 2 Proposed Programmable Data-path (PD)-based Design Approach…………………………………15
2.1 Programmable Data-path (PD)-based Architecture Design...16
2.2 Adder-based Distributed Arithmetic Formulation…..………19
2.3 Spurious Power Suppression Technique (SPST)……………20
2.4 Design Examples of PD-based Design Approach…....……..23
Chapter 3 A Performance-Aware DCT/IDCT IP Core Design Using Scalable-DA Algorithm…………………...29
3.1 Introduction…………………………………………………30
3.2 Design Techniques..…………………………………….…...32
3.2.1 Review of DCT/IDCT and Adder-based DA Formulation.….……32
3.2.2 Evolution of Scalable-DA Algorithm…...………………………...38
3.2.3 Advanced Temporal Refinement (ATR)……………………..……40
3.2.4 Possible Schemes for Performance-Aware Hardware Design……………………………………………………….……41
3.3 Design of the Performance-Aware DCT/IDCT IP Core…….42
3.3.1 Data-path Design…………………………………….……………43
3.3.2 Design of Pre-process/Post-process Units…..………………….…43
3.4 Implementation, Performance Evaluation, and Comparison..45
3.5 Summary……………………………………….……………47

Chapter 4 An Energy-Aware Variable-Length DCT/IDCT IP Design……………………………...………..…… 49
4.1 Introduction………………………………………………… 51
4.2 Proposed Flexible Hardware Solution………………….…...55
4.2.1 Design Idea in the Proposed Flexible Hardware Solution………..55
4.2.2 Design Techniques……………………………………………….. 57
4.3 Design of the Proposed IP Core…………………………….61
4.3.1 Algorithm Derivation and Complexity Analysis for the Variable-Length DCT/IDCT………………….………………….61
4.3.2 Architecture Design of the Proposed IP Core for SA-DCT/IDCT…………...………………...………………........ 66
4.3.3 Instruction Set of the Proposed IP Core………..…………………67
4.3.4 Management of the Interleaved Memory……………………...….70
4.3.5 Development of the Instruction Library for SA-DCT/IDCT…..…71
4.4 Hardware Realization and Energy-Aware IP Implementation………………………………………..……75
4.4.1 The Design Issues of Hardware Realization……………………...75
4.4.2 The Design Issues of Energy-Aware IP Implementation…………77
4.5 Performance Evaluation and Comparison…………………..80
4.6 Summary…………………………………………………………….87
Chapter 5 A High-Performance H.264 Direct 2-D Transform Coding IP Design………………………………... 89
5.1 Introduction………………………………………………...90
5.2 Transform Coding and Previous Works in H.264…………..93
5.3 Proposed Direct 2-D Transform Coding Design for H.264... 96
5.3.1 Proposed Direct 2-D Transform Algorithm…………………….. .96
5.3.2 Proposed H.264 Direct 2-D Transform Architecture Design……101
5.3.3 Considerations of System Integration─Interlaced I/O Schedule.105
5.4 Implementation and Verification……………………….….108
5.5 Performance Evaluation and Comparison…………………112
5.6 Summary……………………………………………….….116
Chapter 6 Spurious Power Suppression Technique (SPST) and Its Applications…………………………...119
6.1 Introduction………………………………………………..120
6.2 Proposed Spurious Power Suppression Technique (SPST)..124
6.3 Architecture Design for SPST……………...……………...128
6.3.1 Design example 1─SPST-based H.264 multi-transform designs.128
6.3.2 Design example 2─An SPST-based versatile IP Core design…..130
6.4 Implementation and Verification………………………….. 133
6.5 Performance Evaluation and Comparison………………... 137
6.6 Summary………………………………………………….. 139
Chapter 7 A Chip Implementation…..…….………………141
7.1 Introduction…..……………………………………………141
7.2 Design Process…………………………….………………142
7.3 Measuring Considerations……………….………………...143
7.4 Measuring Results…………………………….…………...148
7.5 Summary…………………………………………………..150
Chapter 8 Conclusions and Future Works………………..153
8.1 Conclusions………………………………………………..153
8.2 Future Works………………………………………………155
References…………………………………………………...156
Appendix A Supplementary for Performance-Aware DCT/ IDCT IP Design………..……..…………........163
Appendix B Supplementary for Variable-Length DCT/IDCT IP Design……………………………………...167
Publication List……………………………………………..173
Honor…...…………………………………………………...175

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