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研究生:陳賢修
研究生(外文):Shian-Shiou Chen
論文名稱:應用於DS-SSCDMA系統之低必v虛擬擾亂碼同步器設計
論文名稱(外文):Low-Power Pseudo-Noise Code Acquisition IC Design for DS-SS CDMA Systems
指導教授:朱元三
指導教授(外文):Yuan-Sun Chu
學位類別:碩士
校院名稱:國立中正大學
系所名稱:電機工程所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:中文
論文頁數:66
中文關鍵詞:同步擾亂碼虛擬擾亂碼
外文關鍵詞:CDMAWCDMAscramblingsynchronization
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在寬頻分碼多工存取無線通訊系統當中,同步是相當重要的步驟之一。當手機起動時必須要在最短的時間內搜尋到最適當的基地台以取得溝通。在3G系統逐漸的開通以及無線網路的積極發展之下。單一行動設備要求能夠同時使用在3G以及無線網路的需求會越來越高。3G系統之要包含WCDMA以及CDMA 2000,台灣、日本、南韓是同時開放了兩種系統使用執照,而無線網路更是近年來的發展的一個趨勢。由於3G以及IEEE 802.11g在碼同步硬體的設計上有共通的部分。本設計主要是用來完成行動設備與基地台或無線網路存取點之間碼同步的工作,完成碼同步之後系統才能夠接續完成系統的同步。由於在3G系統中所使用的虛擬亂碼長度都很長,所以仍然需要獨立設計硬體來完成,無法單獨的使用單一處理器來完成相關性的偵測。所以本設計就是因為這個原因設計了一個可以完成WCDMA、CDMA 2000、IEEE 802.11g行動設備與基地台或無線網路存取點之間完成同步的硬體設計。這個設計我們也加入了兩種低必v的技術,讓我們所設計的通用型碼同步電路再執行第一種低必v技術WCDMA系統同步時節省了了37.74%到42.47%必v消耗,執行CDMA 2000系統同步時卻增加了4.25%必v消耗,而IEEE 802.11g系統同步時則節省了了37.78%。第二種低必v技術時WCDMA系統同步時節省了11.79%到31.38%必v消耗,執行CDMA 2000系統同步時卻增加了4.4%必v消耗,而IEEE 802.11g系統同步時節省了30.55%。最後我們結合了這兩種低必v方法並加以改良,在WCDMA、CDMA 2000、802.11g這三個系統同步時所節省的必v效果比前兩種低必v效果更好。這一個虛擬亂碼同步器電路工作電壓是1.8V、TSMC 0.18um Mixed Signal (1P6M) CMOS製程製作、晶片核心面積為1655.63*1655.63μm2 。
Synchronization is one of the most important steps in WCDMA system. When MS (Mobile station) powers on, it must synchronize to the appropriate BS (Base station) as soon as possible. Gradually emergent of 3G mobile communication system and wireless LAN constructive developed, the future of having a combination of 3G mobile systems and wireless LAN into an user equipment is expected. There are two major standards (WCDMA, CDMA 2000) in 3G. In Taiwan, Japan and Korea, these two kinds of license has opened to use concurrently. Recently, wireless LAN is becoming more and more common. Since 3G and IEEE 802.11 are based on the same CDMA technology, thus there is common part in the designing of code synchronization hardware. Primarily, our design is to achieve the code synchronization between user equipment and base station or wireless LAN access point, such that, these systems can work on synchronization. Despite the fact that the length of the pseudo-noise code in 3G is too long, so a unique hardware, is needed to instead of a sole processor, to fulfill the requirements. Accordingly, our design wants to work on WCDMA/CDMA 2000, and IEEE 802.11 user equipment. Their activities between access point and base station are manipulated by the code synchronization hardware. Then we joint two kinds of low power technology into the design, that the first low power technology in WCDMA synchronization, power consumption can be reduce from 37.74% to 42.47%, but in CDMA 2000 synchronization power consumption increase 4.25%, in IEEE 802.11b synchronization power consumption reduce 37.78%.The second low power technology in WCDMA synchronization power consumption can be reduce from 11.79% to 31.38%, but in CDMA 2000 synchronization power consumption increase 4.4%, in IEEE 802.11b synchronization power consumption reduce from 30.55%.Finally, we combine theses two low power technology and improve it, in WCDMA、CDMA 2000 and 802.11g synchronization can save more power than last two low power technology. This Pseudo-Noise Code Acquisition IP operating voltage 1.8v、TSMC 0.18um Mixed Signal (1P6M)、Core area 1655.63*1655.63μm2 .
中文摘要 i
英文摘要 ii
誌謝 iii
目錄 iv
圖列 vi
表列 viii
第1章 序論 1
1-1 無線通訊的演進 1
1-2 研究動機 3
1-3 論文概要 4
第2章 背景及相關研究 5
2-1 直接序列展頻分碼多工存取簡介 5
2-2 寬頻分碼多工存取行動通訊系統 7
2-2.1 系統簡介 7
2-2.2 同步碼及同步通道 9
2-2.3 同步的程序以及演算法 14
2-3 CDMA 2000行動通訊系統 18
2-3.1 系統簡介 19
2-3.2 同步碼及同步通道 20
2-3.3 同步的程序以及演算法 23
2-4 IEEE 802.11無線網路通訊系統 24
2-4.1 系統簡介 24
2-4.2 訊框介紹 26
2-4.3 同步的程序以及演算法 29
第3章 電路設計 31
3-1 虛擬亂碼同步之架構設計 31
3-1.1 相關器 31
3-1.2 相關器陣列 32
3-1.3 必v計算電路 34
3-1.4 累加電路 35
3-1.5 峰值偵測電路 36
3-1.6 係數產生電路 36
3-2 系統的操作流程 37
3-3 低必v設計 42
3-3.1 低必v相關器電路 43
第4章 低必v演算電路設計 46
4-1 研究動機 46
4-2 相關研究發展 47
4-3 低必v演算電路架構 49
4-3.1 電路架構 49
4-3.2 偵測電路單元(Detection Logic unit, DL) 49
4-3.3 資料進出控制器單元(Data In-Out Control unit, DIOC) 51
4-3.4 符號延伸補償單元(Sign Extension unit, SE) 51
4-4 實驗數據 52
4-4.1 相關研究比較 52
第5章 實做與分析 54
5-1 晶片設計流程 54
5-2 弁鉣褌?56
5-3 必v分析 57
5-4 面積分析 62
5-4 佈局平面圖 63
參考文獻 64
附錄 66
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[4] Generation Partnership Project, ”FDD: Physical layer procedures,” 3GPP Technical Specification, TS 25.214, V3.3.0, Jun.,2000.
[5] Yi-Pin Eric and Tony Ottosson, ”Cell Search Algorithms and Optimization in W-CDMA,” in Proc. IEEE Veh. Technol. Conf. VTC2000.
[6] Yi-Pin Eric and Tony Ottosson, ”Cell Search in W-CDMA,” IEEE J.Select. Areas Commun., vol. 18, no. 8, pp.1470-1482, Aug. 2000.
[7] Generation Partnership Project 2, ” Physical Layer Standard for cdma2000 Spread Spectrum Systems,” 3GPP2 Technical Specification,C.S0002-D,v1.0, Feb.,2004.
[8] Y.S. Rao and Anil Kripalani, ” cdma2000 mobile radio access for IMT 2000,” International Conference on Personal Wireless Communication, pp. 6 - 15, Feb. 1999.
[9] Jhong Sam Lee, Leonard E.Miller,” CDMA System Engineering Handbook ”, Boston.London : Artech House,1998.
[10] IEEE Std 802.11-1997, “Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications,” Page(s):i-455,1997.
[11] IEEE Std 802.11b-1999, “Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications,” Page(s):i-90,2000.
[12] IEEE Std 802.11g-2003, “Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications,” Page(s):i-67,2003.
[13] Texas Instrument, “TMS320VC5402 Data Sheet,” Aug. 2000.
[14] Texas Instrument, “TMS320C6202 Data Sheet,” Mar. 2004.
[15] Analog Device,”TigerSHARC Embedded Processor ADSP-TS201S Preliminary Technical Data,” Jun. 2003.
[16] BittWare.”B2-AMC News” Jun. 2004.
[17] Junghwan Choi, Jinhwan Jeon, Kiyoung Choi,” Power minimization of functional units by partially guarded computation,” in Proc. ISLPED '00, pp. 26-27, July 2000.
[18] H. Shimada, H. Ando, T. Shimada,” Pipeline stage unification: a low-energy consumption technique for future mobile processors,” in Proc. ISLPED '03, Aug. 2003,pp. 326 – 329.
[19] V. Tiwari, S. Malik, P Ashar, “Guarded evaluation: pushing power management to logic synthesis/design,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 17, Issue: 10, pp. 1051 – 1060, Oct. 1998.
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[21] Junghwan Choi; Jinhwan Jeon; Kiyoung Choi; “Power minimization of functional units by partially guarded computation” Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on 2000 Page (s):131 - 136
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