臺灣博碩士論文加值系統

在本論文中提出應用於直接降頻式接收機子電路且應用於IEEE 802.15.3a 3-10.6GHz 之ultra-wide band 規範，。本論文規劃的接收器子電路主要是以CMOS 0.18 um製程技術來實現，相較於目前兩大系統的接收機架構，本論文所提出的接收機架構使用較少的電路元件更能整合於單晶片上符合未來SOC趨勢，此接收機系統中的電路透過國家晶片系統設計中心提供之製程完成子電路製作，其中包含有超寬頻低雜訊放大器、超寬頻混頻器、以及超寬頻交互偶合式壓控震盪器等架構。而在低雜訊放大器上，輸入匹配使用了Laddy type匹配方式做寬頻匹配，以確保在頻段內輸入和輸出匹配都能低於10dB並使用電感增強方式去提升電路增益以及增益平坦度。而在可調寬頻壓控震盪器上使用了2個壓控震盪器以及2個EHM混波器去實現以達到可產生涵誑W段的訊號，而寬頻混波器架構上採用double balance架構並在輸出使用負電阻電路，用以達到提升電路增益而降低必v消耗。
實際量測結果寬頻低雜訊放大器在2.2到5GHz，有最高必v增益11dB，輸入輸出阻抗匹配小於-10dB，最低雜訊指數6dB，必v消耗43mW。
而VCO部分，量測頻率在3GHz時phase noise 為-120 dBc/Hz、output power
為-4dBm。頻率在4.88GHz時phase noise 為-118 dBc/Hz、output power
為-10dBm。輸出頻率可涵膂BOA band1,3,4,6,7,8,9,10,11,12,13頻段。
混波器量測上，增益在頻段內為5.8～3.6dB，RF, LO return loss分別大於10dB，IP1dB=-16 dBm，IIP3=-5.36dBm

This presented architecture proposes front-end circuits for a direct conversion receivers used in IEEE 802.15.3a system . Comparing with the two receiver architecture of UWB ,we can use less circuit component to implement ultra wideband receiver. and the proposed topology is helpful for System On Chip (SOC) application. This presented receiver circuits is realized in CMOS 0.18um process and includes ultra wideband Low Noise Amplifier(LNA), ultra wideband cross couple voltage control oscillator(VCO) ,and ultra wideband down convert Mixer. We employ the
Negative feedback resistor to achieve gain flatten and use ladder type filter to achieve
Wideband input matching. In ultra wideband VCO design ,we use two cross couple VCO and EHM to accomplish the all band frequency . In the ultra wideband Mixer, we use a gilbert cell topology to accomplish the mixer and we employ a negative resistance technology to enhance the conversion gain.
In the measured data, the LNA chip reveals show the maximum power gain is 11dB and input matching(S11) and output matching (S22) are less than -10dB from 2.2GHz to 5GHz. The minimum noise figure is 6dB. The total power consumption is 43mW.
According to the measurement of the UWB VCO.the phase noise of 3GHz VCO is -120 dBc/Hz and output power is -4 dBm, phase noise of 4.88GHz VCO is -118 dBc/Hz and output power is -10dBm .In addition, the proposed VCO can cover the bands,1,3,4,6,7,8,9,10,11,12 in MBOA system.
In the measured data of UWB Mixer,the conversion is 5.8～3.6dB in 3~10GHz frequency range.The RF and LO port return loss is lower than -10dB in 3~10GHz. And the linearity of Mixer is -5.36dBm, IP1dB is -16 dBm.

中文摘要 3
英文摘要 4
誌謝 5
附圖目錄 7
表目錄 11
第1章 緒論 12
1.1研究動機與目的 12
1.2 UWB發展現況 13
第2章 射頻前端接收器架構 19
2.1窄頻帶射頻前端系統架構 19
2.2 DS-CDMA 以及MB-OFDM 射頻前端系統架構 24
第3章ULTRA-WIDEBAND低雜訊放大器之設計 29
3.1 窄頻低雜訊放大器設計原理與簡介： 29
3.2超寬頻低雜訊放大器之設計 32
3.3模擬結果: 49
3.4晶片量測結果與討論: 51
第4章ULTRA-WIDEBAND壓控震盪器之設計 55
4.1壓控振盪器原理與簡介 55
4.2超寬頻壓控震盪器設計： 62
4.3模擬結果： 76
4.4量測結果與討論： 78
第5章ULTRA-WIDEBAND混波器之設計 83
5.1窄頻混波器原理與簡介 83
5.2超寬頻混波器設計 88
5.3模擬結果: 98
5.4量測結果與討論： 100
第6章結論與未來發展 107
REFERENCE 108

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