臺灣博碩士論文加值系統

在本篇論文中，我們建立了一個使用分散式睡眠電晶體網路架構的電源閘設計流程。我們針對每個叢集量測其瞬間最大電流(Maximum Instantaneous Current)，並且在限制每個叢集電壓降的情況下，設計睡眠電晶體的尺寸大小。
為了避免電路在甦醒時引起的彈跳現象 (supply / ground bounce) 對電路造成的不良影響，因此我們採用甦醒訊號排序的方式來降低電路在甦醒時的最大電流。我們提出了成本函數 ( cost function ) 的觀念來說明不同的甦醒順序會使得電路在甦醒時消耗的必v有所差異，並藉由此成本函數 ( cost function ) 來選擇消耗必v最少的甦醒訊號排序。

In this paper, we build a distributed sleep transistor network power gating design flow. We measure the maximum instantaneous current for every cluster, and design the sleep transistor size in the limited voltage drop condition for every cluster.
In order to avoid supply / ground bounce when circuits wakeup, we use wakeup signal scheduling to reduce the maximum current when circuits wakeup. We propose cost function to explain the different wakeup signal scheduling make circuits wakeup power consumption different and we use the cost function to choose the minimum power consumption wakeup signal scheduling.

第一章 序論 1
1-1 研究動機 1
1-2 研究重點 2
1-3 本論文章節內容 2
第二章 POWER GATING相關研究 4
2-1 POWER GATING簡介及基本定義 4
2-2 POWER GATING操作模式 6
2-2-1 主動模式 6
2-2-2 睡眠模式 7
2-2-3 甦醒 10
2-3 Sleep transistor network 10
2-3-1 CENTRALIZED SLEEP TRANSISTOR DESIGN 11
2-3-2 CLUSTERED-BASED SLEEP TRANSISTOR DESIGN 11
2-3-3 DISTRIBUTED SLEEP TRANSISTOR DESIGN 14
2.4 Wakeup signal scheduling 15
第三章 POWER GATING DESIGN FLOW 20
3.1 Preparation data 20
3.2 Design flow 27
第四章 WAKE SCHEDULING 33
第五章 電路模擬 38
第六章 結論與未來研究方向 40
參考文獻 41

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