臺灣博碩士論文加值系統

本論文以Xilinx VirtexE XCV600E之 FPGA發展版當作發展平台，完成此運動控制器的設計，並配合個人電腦加以控制。在設計上以PC為控制中心，透過I/O介面卡傳輸資料給FPGA，且經過FPGA-Based NURBS插補與FPGA-Based PID控制演算法後搭配Digital to Analog Devices控制伺服馬達，在週邊電路方面以TFPGAT為主體，搭配DAC7744E晶片的使用，以達成體積、面積縮小化。在TFPGAT內部電路規劃將採用硬體描述語言(Verilog HDL)來設計，以TFPGAT來取代解碼電路和週邊電路，可用模組化結構設計電路，以有效降低設計成本，並提昇整體運作的速度。

本系統為一完整、有系統組合彈性及易於擴展之運動控制器。系統模型實現了硬體電路結構之過程。在元件的使用上，其重複使用性及擴充性能也提昇了系統設計上及使用上的效率。最後，並利用X-Y 平台來加以驗證此運動控制系統的完整性及實用性。

In this paper, a novel FPGA (Field Programmable Gate Array) based motion controller is proposed to realize real-time NURBS (Non-Uniform Rational B-Spline) interpolation and servo control on an FPGA chip, and high-speed communication with PC. The last generation of FPGA-based motion controller utilizes its parallel computing power to perform the Cox-de Boor algorithm and the IIR (Infinite Impulse Response) algorithm in real-time, however, the PC client must download the parameters of a NURBS curve to the FPGA chip off-line before it runs. The proposed FPGA-based motion controller is capable of performing high-speed communication with PC in about 8M Hz, and the PC client can transmit different NURBS curves to the FPGA chip through the PCI DIO card on-line. Numerical simulations and experimental tests using an X-Y table verify the outstanding communication performance of the FPGA-based motion controller. The result indicates that NURBS interpolation, servo control, and high-speed communication can be achieved in real-time for the FPGA-based motion controller which is highly critical to the success of high-speed and high-accuracy motion control.

目錄
圖目錄 iv

表目錄 ix

第一章 緒 論 1

1-1 前言 1

1-2 研究動機與目的 2

1-3 文獻回顧 4

1-4 研究方法 7

1-5 論文架構 10

第二章 FPGA硬體架構與設計11

2-1 數位系統電路簡介 11

2-2 FPGA硬體架構之介紹 12

2-3硬體描述語言的重要性 19

2-4 Verilog硬體描述語言的特性 22

第三章 PC與FPGA傳輸介面之設計 23

3-1 傳輸系統之硬體裝置 25

3-2 即時子作業系統之使用 28

3-3 PC與FPGA之交握傳輸(Handshake)協定 30

第四章 FPGA-Based插補器系統架構 37

4-1 參數式曲線/曲面: NURBS簡介 38

4-2 Cox-de Boor 演算法之介紹 41

4-3 FPGA插補器內部電路模組之設計 44

第五章 FPGA-based 控制器系統架構 48

5-1 伺服控制系統鑑別 50

5-2 FPGA回授處理電路之實現 58

5-2.1 四倍頻解碼電路之設計 59

5-2.2 位置計數電路之設計 63

5-2.3 速度檢出電路之設計 64

5-3 FPGA伺服控制器之設計與實現 66

5-3.1 位置控制器之設計 67

5-3.2 速度控制器之設計概念 72

5-3.3 DAC的驅動時序與運作原理78

第六章 整體系統實現與結果分析 83

6-1 實驗發展系統環境之介紹 83

6-2系統模擬與整體實驗結果 88

6-3實驗結果分析 111

第七章 結論及未來研究方向 113

7-1 結論 113

7-2 未來研究方向114

參考文獻 116

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