臺灣博碩士論文加值系統

隨著積體電路製程技術日益精進，電晶體通道變短，使電路可以更快速的工作；門檻電壓變低、工作電壓下降，功率消耗減少；單位面積內電晶體密度變高。然而在高密度IC內，電路與電路之間距離縮短，使得電路間相互影響力變大。隨著工作電壓下降，使得雜訊免疫能力降低，雜訊對於訊號相對影響力變大。因此對於雜訊的研究顯得愈來愈重要。
本論文提出兩種新的量測電壓源雜訊架構﹕
1. 將傳統的峰偵測器加以改良後，應用在偵測電壓源雜訊上。其特色是可在某時段內，將最大的雜訊值偵測並將其電位保持住，以便於下一級電路處理，使得下一級電路對工作速度的要求限制變低。可在10% ~ 45% VDD範圍內，偵測到1GHz雜訊。在電流相同情況下，本篇論文所提出電路比傳統電路的速度提升兩倍。
2. 第二個偵測電路為利用邏輯閘在信號傳輸時，因雜訊大小而產生延遲快慢之原理，來偵測時脈切換時，電壓源上所產生的雜訊。可偵測4GHz之雜訊相對大小(在時脈訊號為1GHz)。此電路功率小且面積小，可散佈於晶片內，用於偵測不同位置之雜訊大小。

With the advancement of processing technology of integrated circuits(ICs), the channel length of transistor becomes shorter and the circuit can work faster. The threshold voltage and power supply both become lower to reduce the power consumption. However, the density per unit area becomes higher. In high density ICs, the spacing is shortened between circuits and therefore the interaction effect increases. The power supply is lowered, but the noise becomes relatively larger. The noise immunity is greatly reduced. Therefore, the research of noise effects becomes more and more important.
Two new methods have been proposed in this thesis to detect the power supply and ground noise:
1. A modified peak detector sample and hold circuit is presented first. The proposed circuit can detect the maximum noise and holds its value. The circuit is verified able to detect the power supply and ground noise of 1GHz of the magnitude from 10% to 45% VDD. As compared to the prior art, both the detection range and speed are improved significantly.
2. Another proposed circuit can detect the power and ground noise of the frequency up to 4GHz. With small power and area for this circuit, the proposed circuit is easily to be arranged in a chip to detect the noise magnitude of different blocks.

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誌謝…………………………………………….………..…….……….. iv
中文摘要……………………………………………………………........v
英文摘要……………………….….…………….……….……….…......vi
目錄..........................................................................................................vii
圖目錄........................................................................................................x
表目錄..................................................................................................... xv
第一章 緒論……………………………………………………………1
1.1 研究背景與動機……………………….………….……………1
1.1.1 研究背景…………………………………………………..1
1.1.2 雜訊的導因與效應………………………………………..2
1.1.3 研究動機…………………………………………………..5
1.2 研究方向………………………………………………………..6
1.3 論文結構……..……………………….………….……………..6
第二章　雜訊偵測器之系統與分析……………………………………7
2.1 現有電路架構分析……………………………………………...7
2.1.1 內建式探測電路…………………………………………..7
2.1.2 電壓下降偵測器…………………………………………..9
2.1.3 自身檢驗偵測技術………………………………………11
2.1.4 雜訊監測電路……………………………………………13
2.2 討論…………………………………………………………….15
第三章　峰值偵測器的改良與雜訊偵測上的應用…………..………16
3.1 傳統電路……………………………………………………….16
3.2 改良式電路偵測工作電壓凸波雜訊………………..……...…20
3.2.1 峰值偵測電路配一源極隨耦器…………..……………..20
3.2.2 回授技巧的應用……………………………………...….27
3.2.3 補償電壓電晶體……………..……………………..........30
3.3 其它類型雜訊處理技術……………………………………….32
3.3.1 接地點壓降……………………………………………..32
3.3.2 工作電壓壓降、接地點凸波………………..………….33
第四章 電路模擬與比較………………………………………………35
4.1 偵測1GHz以上之偵測電路…………………….…….……….35
4.2 電路比較……………………………………………………….43
第五章 量測電路設計及佈局模擬……………………………………46
5.1 量測電路設計………………………………………………….46
5.2 電路佈局……………………………………………………….55
5.3 模擬結果……………………………………………………….58
5.4 量測考量……………………………………………………….64
第六章 總結及未來研究方向…………………………………………67
參考文獻………………………………………………………………..68

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