臺灣博碩士論文加值系統

本研究論文以Verilog硬體描述語言設計八位元微處理器，在此，我們透過重新組合輸入時脈的方式，進而將指令週期縮短為兩個輸入時鐘週期，提昇了CPU的執行效率。為避免使用者因為對硬體架構的不熟悉而導致程式設計的錯誤，本設計亦改良了記憶體的管理方式，即將記憶體中的特殊功能暫存器位址改變於FFH之後，提高了程式撰寫的便利性。此外，我們也加入外部中斷的功能，並使用一開關做簡單切換。除了以FPGA進行微處理器硬體電路設計驗證外，本研究更搭配線路模擬器，形成一PC-FPGA整合開發系統，如此便可透過在PC上撰寫的組合語言，作立即性的程式功能模擬。根據本研究之結果，針對此一微處理器，未來可以透過加入各式不同的模組，以符合各種不同需求的應用，並且可以朝向矽智財（SIP）邁進。

In this thesis, we use Verilog Hardware Description Language (HDL) to design an 8-bit RISC microprocessor. Here, we first efficiently reorganize the input clock scheme. In addition, using the pipelining structure the instruction cycle is further reduced to two input clocks. As a result, the performance efficiency of the designed CPU is enhanced. In order to avoid possible mistakes arising during the programming task, we rearrange the memory management of the designed CPU by changing the address of the special function register to FFH. We also include an external interrupt with a simple switch button in our design. The designed hardware circuit of the CPU is verified using FPGA. Moreover, we also incorporate an “In Circuit Emulation” (ICE) into our design so that one may write the assembly language and then immediately verify it in an integrated environment on PC. According to the results of this thesis, for future development a variety of modules may be further integrated into our design to meet a number of different requirements/applications, towards a Silicon Intellectual Property (SIP).

指導教授推薦書……………………………………………….………Ⅰ
口試委員審議書…………………………………………….…………Ⅱ
授權書…………………………………………………….……………Ⅲ
誌謝………………………………………………………...…………..Ⅳ
中文摘要……………………………………….…………………...….Ⅴ
英文摘要…………………………………………………….…...…….Ⅵ
第一章 緒論……………………………………………..……….…. 1
1.1 研究背景與相關研究…………………………………………... 1
1.2 研究目的與動機…………………………………………….….. 4
1.3 論文架構簡介…………………………………………….…….. 6
第二章 微處理器架構簡介……………...…………………..…..…. 8
2.1 精簡指令集微處理器架構……………………………………. 8
2.2 精簡指令集微處理器指令歸納與分解………………………. 15
第三章 改良式精簡指令集微處理器架構簡介………………….. 24
3.1 時脈改良………………………………………………………. 24
3.2 記憶區塊規劃………………….…..………………………….. 25
3.3 指令擴充…….………………………………………………… 28
3.4 架構軟體模擬與可程式邏輯驗證………….………………… 32
第四章 微處理器實體測試結果與探討………………………….. 35
4.1 RTL Codes模擬結果………………………………………… 35
4.2 硬體測試結果………………………………………………… 44
第五章 結論與未來展望…………………………………………. 51
5.1 結論………………………………………………..….............. 51
5.2 未來展望……………………………………............................ 52
附錄A……………………………….…………………………......... 53
參考文獻…………………………………………………….............. 57

參考文獻
[1] Qing-Lan Lv,Ping Li，“A 8-bit MCU design using a four-pipeline architecture” Communications, Circuits and Systems and West Sino Expositions, IEEE 2002 International Conference on Volume 2, 29 June-1 July 2002 Pages: 1462 - 1465 vol.2

[2] Yamin Li, “Computer organization ans system architecture”. Beijing, Tsinghua University Press, 2000

[3] Weimin Zheng, Zhishong Tang, “Computer system architecture (second edition)”, Beijing, Tsinghua University Press, 1998

[4] Guangdi Li, Yuexiu Zhu, Xiushan Wang, “The basis of microcontroller (revision)”, Beijing, Press of Beijing University of Aeronautics and Astronautics, 2001

[5] Microchip Technology Inc. 8-Bit CMOS Microcontrollers with A/D Converter, version DS30390D., Microchip Technology Inc., 1996

[6] Microchip Technology Inc. 18/20-Pin, 8-Bit CMOS Microcontrollers with 10/12-bit A/D, version DS41120B., Microchip Technology Inc., 2002


[7] Microchip Technology Inc. 8-Bit CMOS Microcontrollers with A/D Converter, version DS30390E., Microchip Technology Inc., 1997

[8] 何信龍，李雪銀，PIC16C7X入門與範例應用，初版二刷，台北，全華科技圖書股份有限公司，民國九十年。

[9] 趙春棠，PIC單晶片學習秘笈以PIC 16F877為例，初版，台北，全威圖書有限公司，民國九十一年，ISBN：, 9867953347。

[10] Kyoung-soo Kim, Ju-sung Park, “Study on micro controller design and verification methodology” Science and Technology, 2003. Proceedings KORUS 2003. The 7th Korea-Russia International Symposium on Volume 2, Date: 28 June-6 July 2003, Pages: 228 - 233 vol.2 IEEE

[11] Yu Ying, Zhou Lei, Min Hao “Design and VLSI implementation of an asynchronous low power microcontroller” ASIC, 2001. Proceedings. 4th International Conference on Date: 2001, Pages: 797 - 799 Digital Object Identifier 10.1109/ICASIC.2001.982683

[12] Hauck, “Asynchronous Design Methodologies: An Overview” Proceesings of the IEEE, Vol.83, No.1,pp69-93, Jan, 1995

[13] G. Gopalakrishanan, “Guest Editor’s Introduction to the Special Issue on Asynchronous Systems”, Integration, the VLSI Journal 15(1993), pp223-239

[14] S. B. Furber, etc, “AMULET2e: An Asynchronous Embedded Controller”, Proceedings of the IEEE, Vol.87, No.2,Feb 1999, pp243-255

[15] David A. Patterson, John L. Heunessy, 1994, Computer Organization & Design, Hardwareisoftware Interface, Morgan Kaufmann

[16] Pran Kump, Taher Abbasi,1995, Logic Synthesis using Synopsys, Kluwer Academic Publishers

[17] Eli Sternheim Rajvir Singh, Rajeev Madhavan, Yatin Trivedi, 1993, Digital Design and Synthesis with Verilog HDL, Automata Publishing Company