臺灣博碩士論文加值系統

中文摘要
本論文使用TSMC 0.18μm CMOS 製程以研製“應用於UWB無線射頻系統之前端電路整合”。在接收機的規劃上，為因應超寬頻系統之需要，著重於低雜訊與低功率消耗之特點，並將射頻訊號應用於3.1~10.6GHz 之UWB 頻帶，所設計之電路有：低雜訊放大器(LNA)、混頻器(mixer)及壓控振盪器(VCO)等。
超寬頻壓控振盪器(UWB)，其模擬結果為：輸出頻率6.5~10.4GHz、相位雜訊-95 ~ -112dBc/Hz@1MHz、調諧範圍為3.9GHz、輸出訊號功率-5.8 ~ 3.7dBm、功率消耗13.8mW。全頻帶接收器，其模擬結果為：轉換增益9.743 ~ 16.845dB、雜訊指數3.75 ~ 7.233dB、功率消耗22.45mW、LO 至IF 隔離度48 ~ 64dB、LO 至RF 隔離度86.5 ~ 119.8dB、1dB 增益壓縮點-36 ~ -30dBm、三階截斷點17.5 ~ 24.8dBm 。所有電路模擬均使用安捷倫之Advanced Design
System(ADS)設計完成。

ABSTRACT
This thesis presents the development of CMOS RFICs for “Integration of 3.1~10.6GHz Front-End Receiver for UWB System” with TSMC0.18μm CMOS process. For the Ultra-wide Band system application, the CMOS RF IC is focused on low power consumption and low noise, and operated at 3.1~10.6GHz UWB. The CMOS RFICs include LNA, mixer and VCO.

UWB VCO operates around 6.5 GHz to 10.4 GHz with -95 ~ -112dBc/Hz@1MHz phase noise, tuning range of 3.9 GHz, output power of-5.8 ~ 3.7dBm, and power consumption of 13.8 mW. The RF Front-End is applied for UWB Wireless Receivers. The total DC power consumption is just 22.45mW with a supply source of 7.4mA and 1.8V. The simulated performances of the topology are conversion gain of 9.743 ~ 16.845 dBm, noise figure of 3.75 ~ 7.233 dB, power consumption of 22.45 mW, LO to IF isolation of 48 ~ 64 dB, LO to RF isolation of 86.5 ~ 119.8 dB, P1dB of -36 ~ -30dBm, and IIP3 of 17.5 ~ 24.8dBm. All circuits are designed and simulated by Advanced Design System (ADS).

目錄
中文摘要 Ⅰ
英文摘要 Ⅱ
致謝 Ⅲ
目錄 Ⅳ
圖目錄 Ⅶ
表目錄 Ⅹ
第一章、緒論....................................................................1
1.1 UWB 研究背景…...........................................................1
1.2 論文架構....................................................................................6
1.3 RF前端電路參考規格.................................................................7
第二章、電路架構…………..………………………..…………………9
2.1外差式接收機………………………………………….……….9
2.2直接轉換接收機…………………………………….………...15
2.2.1直流偏移(DC offset)………………………………..11
2.2.2顫動雜訊(Flicker noise)……………..……………16
2.2.3偶次諧波干擾(Even order distortion)…………..16
2.2.4正交與同相訊號的不平衡(I/Q mismatch)…………17
2.3寬中頻與低中頻接收機………………………………..........17
第三章、UWB CMOS壓控振盪器……………………..……………21
3.1簡介………………………………………………….............21
3.2 CMOS壓控振盪器之原理……………………………........21
3.2.1回授式壓控振盪器……………………………….......21
3.2.2反射式壓控振盪器…………………………………...23
3.3相位雜訊(Phase Noise)……………………………….......24
3.3.1相位雜訊之定義……………………………................24
3.3.2相位雜訊對無線收發機之影響………………............25
3.4 振盪器之相位雜訊分析…………………............................27
3.4.1 非時變模型(Time Invariant) ……….…................27
3.4.2時變模型(Time Variant) ….…...................................29
3.5 UWB CMOS壓控振盪器…………………………………...36
3.5.1模擬結果 ……………………………………………..38
3.5.2量測結果………………………………………………42
3.6 結果與討論…………………………………………………44
第四章、UWB 收發機CMOS 射頻前端電路……………………....46
4.1 UWB 收發機射頻前端電路簡介………………………….46
4.2 接收機效能參數…………………………............................47
4.2.1 雜訊指數(Noise Figure) ………………………….47
4.2.2 交互調變失真(IMD) …………………………...........50
4.2.3 1dB 增益壓縮點(1dB Compression Point) ………52
4.3 低雜訊放大器………………………………………………53
4.3.1 低雜訊放大器設計簡介…………………………......53
4.3.2 低雜訊放大器(LNA)基本架構…………………........53
4.3.3 前端帶通濾波器…………………………………......54
4.4 混頻器…………………........................................................56
4.4.1 單端平衡混頻器..........................................................58
4.4.2 CMOS 電流抽出混頻器................................................59
4.5 收發機射頻前端電路............................................................61
4.5.1 射頻前端電路之模擬結果..........................................64
4.5.2 量測與結果..................................................................68
第五章、結論…………………………………………………………..69
5.1結論………………………………………………..………....69
5.2未來展望……………………………………………..………70
參考文獻……………………………………………..…………………71
附錄……………………………………………………………………..74

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