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研究生:陳文俊
研究生(外文):Wen Chun Chen
論文名稱:砷在絕緣層上矽之摻雜劑量損失研究
論文名稱(外文):Investigation of Arsenic Dose Loss in Silicon on Insulator
指導教授:張睿達
指導教授(外文):Ruey Dar Chang
學位類別:碩士
校院名稱:長庚大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:英文
論文頁數:46
中文關鍵詞:絕緣層上矽界面偏析離子植入劑量損失去吸附/吸附
外文關鍵詞:silicon on insulatorinterface segregationarsenicion implantationdose lossdetrapping/trapping
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雜質在半導體元件內的擴散是非常重要的。在此次研究中,150Å的氧化層成長於矽塊材和絕緣層上矽的晶片,並以80keV的能量將5×1014 /cm2的砷離子植入晶片內。隨後使用爐管對晶片施以950℃不同時間的退火,並藉由二次離子質譜儀的分析,來了解砷離子劑量損失的情形。實驗結果發現,試片所測得之阻值變化與砷離子劑量的損失有關。而對業界常用的製程模擬器而言,如使用其介面偏析之 去吸附/吸附 預設比值則會低估砷離子的劑量損失。針對矽塊材和絕緣層上矽的試片,我們已校正其介面偏析的模型參數,以與量測得到之劑量損失和阻值相符。
Impurity distribution inside semiconductor devices is important. In this study, 150Å oxide was growth on bulk silicon and silicon on insulator (SOI) wafers. Arsenic ions were implanted into wafers at 80keV with a dose of 5×1014 /cm2. Subsequent annealing was performed by a conventional furnace at 950℃ for different times. The dose loss of arsenic was analyzed by secondary ion mass spectrometer. The change of measured sheet resistances was found to be correlated with arsenic dose loss. The default detrapping/trapping ratio for interface segregation in industry standard process simulator under estimates the arsenic dose loss. The interface segregation model was calibrated to fit the measured dose loss and sheet resistance for both bulk silicon and SOI samples.
中文摘要
Abstract
Chapter 1. Introduction
1-1 The Motivation of Study
1-2 Ion Implantation
1-3 Diffusion
1-4 Dose Loss and Interface Segregation
1-5 Silicon on Insulator
Chapter 2. Experimental Procedures
2-1 Sample preparation
2-2 Transmission Electron Microscope Observation
2-3 Arsenic Depth Profiling Analysis
2-4 Sheet Resistance Measurements
Chapter 3. Results and Discussion
3-1 TEM Observation
3-2 Arsenic Depth Profiling Analysis
3-3 Sheet Resistance Measurements
Chapter 4. Simulation
4-1 The Simulation of Arsenic Redistribution Profile
4-2 The Simulation of Sheet Resistance
Chapter 5. Conclusion
Reference
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