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研究生:蕭淵鍊
研究生(外文):HSIAO,YUAN-LIEN
論文名稱:IEEE802.11aCMOS頻率合成器設計
論文名稱(外文):DESIGN of IEEE 802.11a FREQUENCY SYNTHESIZER
指導教授:田慶誠田慶誠引用關係
指導教授(外文):TIEN,CHING-CHEN
學位類別:碩士
校院名稱:中華大學
系所名稱:電機工程學系(所)
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:94
語文別:英文
論文頁數:71
中文關鍵詞:頻率合成器鎖相迴路
外文關鍵詞:FREQUENCY SYNTHESIZERPLLPHASE LOCK LOOPIEEE 802.11a
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論文摘要由於頻率合成器在現今科技日新月異的科技生活中扮演著不可或缺的角色,加上頻率合成器的應用廣泛,例如:電視機的選台器、無線網路卡等只要關乎頻率的鎖定都有它的存在,本論文的目的在於介紹頻率合成器的理論分析和實際設計一個頻率合成器的設計過程。本設計符合IEEE 802.11a無線區域網路頻率合成器規格。以鎖相迴路為機制的頻率合成器採用整數N除頻器並且可輸出5.15~5.35GHz穩定的輸出信號。本論文第一部分將針對頻率合成器電路架構做介紹,並將頻率合成器作細部的功能介紹。由於相位雜訊是射頻混頻的主要問題所在,所以第二部份將對相位雜訊做探討。第三部份則是本設計的模擬和晶片的量測。 在本論文所設計的頻率合成器使用台積電0.18 um 1p6m CMOS製程,並使用ADS電腦輔助軟體來模擬所設計的電路,使用MaxplusII來先作數位電路驗證。目前頻率合成器的設計大部分朝向降低消耗功率和高整合密度,故本論文也提出一個頻率合成器消耗功率與本論文所設計作比較。 相位雜訊對通訊系統來說是非常重要的,尤其對提供一個升降頻的穩定頻率來說,如果相位雜訊不合乎規格,容易使後級接收到的頻率被相位雜訊所干擾。本論文對相位雜訊的壓抑,也提出了有效的解決的方法。
AbstractDue to the frequency synthesizer plays an indispensable role in the scientific and technological life of science and technology with rapid change now, in addition, the application of the frequency synthesizer is extensive, for example: Television select platform device, so long as wireless network card, and etc. concern locking of frequency have existence of it, the purpose of this thesis lies in recommending the theory of the frequency synthesizer to analysis and the actual design process of a frequency synthesizer. The design meets the IEEE 802.11a WLAN Frequency synthesizer specification. The frequency synthesizer based on phase-locked-loop adopts integer-N divider and provides 5.15~5.35GHz stable output signal to meet the IEEE 802.11a lower and middle bands. The first part in the work presents the architecture and the function of the frequency synthesizer. The second part is to discuss the phase noise in frequency synthesizer because phase noise is the major problem in the RF front end. The third part is present the simulation and the measurement results. In this frequency synthesizer designed of thesis uses Taiwan Semiconductor Manufacturing Co. 0.18 um 1p6m CMOS to realize, and uses ADS computer's auxiliary software to imitate the circuit designed, proves that the respect uses “MaxplusII”. The most orientations of design the frequency synthesizer tends to lower power consumption and high density at present, so the thesis proposes that a frequency synthesizer consumes power and a thesis to design and make comparisons. Phase noise is very important to communication system, especially in offering a steady frequency of going up and down. If the phase noise does not meet to the specification, it is easy to grade of frequency reached to receive interfere by the phase noise. The effective methods of reducing phase noise are proposed in the thesis.
ContentsChapter 1 Introduction 9 1-1 Motivation and Goal 9 1-2 Thesis Outline 9 1-3 General Architecture and Operational Principle 9 1-3-1. Application of PLL: 9 1-3-2 Basic PLL architecture: 12 Chapter 2 PFD and Charge Pump 15 2-1 Phase Frequency Detector (PFD) 15 2-2 Charge Pump 18 2-3 Dead Zone Problems: 23 Chapter 3 Loop Filter, Voltage Control Oscillator and Phase Noise 25 3-1 Loop Filter 25 3-1-1 First Order Loop Filter 26 3-1-2 Second Order Loop Filter 26 3-1-3 Third Order Loop Filter 27 3-2 Bode Plot 32 3-3 Phase Noise 34 3-3-1 Noise Source in PLL 34 3-3-2 PLL Composite Phase Noise 38 3-3-3 Phase Noise Measurements 39 3-3-4 Spurious Suppression 39 3-3-5 Loop Response Simulation 40 Chapter 4 Frequency Divider 41 4-1 Divider 41 4-1-1 Function of Divider 41 4-1-2 Divider Block 42 4-1-3 Preamp 44 4-1-4 Pre-Divide by Two Circuit 46 4-2 Pulse-Swallow Divider 48 4-2-1 Dual-Modulus Pre-Scaler 49 4-2-2 P-counter and S-counter: 50 Chapter 5 Design Flow, Simulation Results, and Chip Implement 52 5-1 Design Flow 52 5-2 Simulation Results 53 5-2-1 Simulation Results for PFD, Charge Pump and Loop Filter 53 5-2-2 Simulation Results of Pre-Scaler 57 5-2-3 Simulation Results of Pulse-Swallow Divider 60 5-2-4 Settling Time 61 5-2-5 Simulation Results of Whole PLL Close Loop 62 5-3 Chip Implement and Layout Consideration 65 Chapter 6 Conclusion and Future works 68 6-1 Conclusion 68 6-2 Future works 69 Bibliography 70
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