臺灣博碩士論文加值系統

離散小波轉換目前成功地應用在各種領域，包括信號分析、信號壓縮、圖像識別、以及數值分析。加上離散小波轉換是一種多重解析度的分解，可將信號分解出不同的頻帶，根據這些重要的特性，便可針對其特性做最佳的處理，而達到更好的影像品質。目前已有許多關於傳統離散小波轉換(DWT)架構的文章被提出，但是對於這些傳統的架構所需要得計算量相當的大。因此，在1996 年，Sweldens 提出了新的小波轉換-提昇式離散小波轉換(Lifting-based DWT)，相較於傳統濾波器的架構，其所需要得硬體將大大的減少，最主要的原因是因為提昇式離散小波轉換架構是利用Polyphase 架構將矩陣拆解成上三角和下三角以及對角矩陣的乘積。 本論文主要說明二維順向與反向提昇式離散小波轉換架構利用5/3 濾波器實現，利用平行及管線化的方式完成整體的架構，此外我們也利用適當的時序排程和暫存器配置的方式，將電路中暫存器數目進行最佳化縮減。以及乘法器的使用將利用位移取代乘法器，減少硬體使用面積。本篇論文設計的架構具有無乘法器、100%的硬體使用率、較低複雜度的控制電路、規則的資料流。

The discrete wavelet transform (DWT) has proven to be a useful technique for a wide range of applications including signal analysis, signal compression, pattern recognition and numerical analysis. The DWT decomposes signals into different frequency bands, and performs a multiresolution analysis. Many papers proposed the algorithms and architecture of DWT, but they require massive computation. In 1996, Sweldens proposed a new lifting based DWT architecture with much fewer hardware requirements compared to the conventional approaches. The main idea of the lifting based DWT is to factorize the polyphase matrix of wavelet filter into a sequence of alternating upper and lower triangular matrices and diagonal matrix. Usually the lifting–based DWT and IDWT requires less computation compared to the convolution-based approach. However, the savings depend on the length of the filters. During the lifting implementation, no-extra memory buffer is required because of the in-place computation feature of lifting. This is particularly suitable for the hardware implementation with limited available on-chip memory. In this paper, the 2-D DWT and IDWT architectures are proposed. The architectures for the lifting-based discrete wavelet transform (DWT) and inverse discrete wavelet transform (IDCT) using 5/3 wavelet filter are proposed. The proposed parallel and pipelined architectures consist of a horizontal filter (HF), or inverse horizontal filter (IHF), and vertical filter (VF), or inverse vertical filter (IVF).The delays for the forward and inverse wavelet architectures are reduced.

英文摘要．．．．．．．．．．．．．．．．．．．．．．．．．Ⅰ摘要．．．．．．．．．．．．．．．．．．．．．．．．．．．Ⅱ致謝．．．．．．．．．．．．．．．．．．．．．．．．．．．Ⅲ目錄．．．．．．．．．．．．．．．．．．．．．．．．．．．Ⅳ圖目錄．．．．．．．．．．．．．．．．．．．．．．．．．．Ⅵ表目錄．．．．．．．．．．．．．．．．．．．．．．．．．．Ⅸ第一章 導論 ．．．．．．．．．．．．．．．．．．．．．．．1 1.1 研究背景與動機 ．．．．．．．．．．．．．．．．．．1 1.2 相關研究 ．．．．．．．．．．．．．．．．．．．．．3 1.3 研究步驟及方法 ．．．．．．．．．．．．．．．．．．4 第二章 離散小波轉換 ．．．．．．．．．．．．．．．．．．．5 2.1 前言 ．．．．．．．．．．．．．．．．．．．．．．．5 2.2 Haar 離散小波轉換 ．．．．．．．．．．．．．．．．．7 2.3 旋積分式(convolution)離散小波轉換．．．．．．．．．．9 2.4 提昇式離散小波轉換．．．．．．．．．．．．．．．．16 第三章 5/3 濾波器之提昇式離散小波轉換 ．．．．．．．．．．22 3.1 前言．．．．．．．．．．．．．．．．．．．．．．．22 3.2 5/3 濾波器之提昇式離散小波轉換 ．．．．．．．．．．23 3.2.1 雙輸入摺疊式分解架構．．．．．．．．．．．．．．29 3.2.2 效能比較．．．．．．．．．．．．．．．．．．．．43 3.3 5/3 濾波器之提昇式離散小波反轉換 ．．．．．．．．．45 3.3.1 雙輸入摺疊式合成架構．．．．．．．．．．．．．．47 第四章 模擬結果．．．．．．．．．．．．．．．．．．．．．58 4.1 設計流程圖 ．．．．．．．．．．．．．．．．．．．58 4.2 Verilog 模擬結果．．．．．．．．．．．．．．．．．．59 4.3 Matlab 模擬結果．．．．．．．．．．．．．．．．．．64 第五章 結論．．．．．．．．．．．．．．．．．．．．．．．67 參考文獻．．．．．．．．．．．．．．．．．．．．．．．．．69 發表論文列表．．．．．．．．．．．．．．．．．．．．．．．73

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