臺灣博碩士論文加值系統

本論文探討可變增益低雜訊放大器（VGLNA）與主動式平衡－非平衡阻抗轉換器（Active Balun）之設計，應用於IEEE 802.11a 無線區域網路5GHz CMOS射頻電路。此電路具有三種可調的增益模式，並可提供12 dB之動態範圍。電路模擬在高增益模式下，雙輸出端之有效增益S21∕S31分別為24.306 dB/23.798 dB，雜訊指數為2.507 dB∕2.539 dB，線性度之IP1dB分別為-23.5 dBm∕-24.5dBm，IIP3為-26.377 dBm∕-27.775 dBm；在中增益模式下，雙輸出端之有效增益分別為19.449 dB∕18.942 dB，雜訊指數為2.728 dB∕2.818 dB，線性度之IP1dB分別為-18.5 dBm∕-20.5dBm，IIP3為-21.856 dBm∕-23.145 dBm；在低增益模式下，雙輸出端之有效增益分別為13.531 dB、13.026 dB，雜訊指數為3.459 dB、3.739 dB，線性度之IP1dB分別為-13.5 dBm∕-14.5dBm，IIP3為-16.587 dBm∕-17.714dBm，Gain 與Phase Mismatch分別在1 dB∕3°內，而且維持在預定的規格之下。電路最大消耗功率（Power Consumption）為37.314 mW。電路模擬使用台積電（TSMC）提供的0.18 um CMOS process製程。

This thesis presents design of a 5.25GHz CMOS RFIC of variable-gain low noise amplifier (VGLNA) with active balun for WLAN applications. This work has three stages of the tunable gain to supply system the dynamic range of 12 dB. In the high gain mode, the results of two output ports are simulated 24.306 dB∕23.798 dB with available power gain of S21∕S31, 2.507 dB∕2.539 dB of noise figure, -23.5 dBm∕-24.5dBm of linearity IP1dB, -26.377 dBm∕-27.775 dBm of IIP3. In the medium gain mode, the results of two output ports are simulated 19.449 dB∕18.942 dB with available power gain of S21∕S31, 2.728 dB∕2.818 dB of noise figure, -18.5 dBm∕-20.5dBm of linearity IP1dB, -21.856 dBm∕-23.145 dBm of IIP3. In the low gain mode, the results of two output ports are simulated 13.531 dB∕13.026 dB with available power gain of S21∕S31, 3.459 dB∕3.739 dB of noise figure, -13.5 dBm∕-14.5dBm of linearity IP1dB, -16.587 dBm∕-17.714 dBm of IIP3. The mismatch of gain and phase of two output ports are kept 1 dB∕3°within the predictable of performance. The simulated power consumption of circuit is 37.314 mW. This work is simulated by using the TSMC standard 0.18 μm CMOS technology.

第一章 緒論
1.1 研究動機………………………………………………………...1
1.2 章節規劃………………………………………………………...4
第二章 無線射頻接收機系統架構與規格訂定
2.1 簡介……………………………………………………………...5
2.2 無線射頻接收機系統架構……………………………………...6
2.2.1 超外差式接收機（Super-Heterodyne Receiver）………...6
2.2.2 直接降頻式接收機（Direct-Conversion Receiver）……..8
2.3 無線射頻接收機效能與參數要求…………………………….13
2.3.1 接收機射頻接收相關規範……………………………….13
2.3.2 接收機射頻效能參數與通訊系統規範間之關係……….14
2.3.3 接收機射頻效能參數…………………………………….15
2.3.3.1 雜訊指數（Noise Figure, NF）…………………15
2.3.3.2 交互調變失真（Inter-modulation Distortion, IMD）
與三階截止點（IP3）………………………...21
2.3.3.3 1dB增益壓縮點（1dB Compression Point）…..23
2.4 結論…………………………………………………………….25
第三章 可變增益低雜訊放大器與主動式Balun之設計
3.1 簡介…………………………………………………………….26
3.2 設計流程……………………………………………………….27
3.3 CMOS低雜訊放大器電路架構……………………………….28
3.3.1 簡介………………………………………………………28
3.3.2 共源疊接（Common-Source Cascode）放大器架構……28
3.3.3 CMOS低雜訊放大器雜訊模型…………………………29
3.3.4 最佳電晶體寬度之選擇…………………………………32
3.4 可變增益低雜訊放大器電路與主動式Balun架構…………..34
3.4.1 電路架構比較……………………………………………34
3.4.2 電路架構簡介……………………………………………36
3.4.3 電路設計流程……………………………………………37
3.5 結論…………………………………………………………….43
第四章 模擬結果與量測考量
4.1 簡介…………………………………………………………….44
4.2 鎊線（Bond-wire）與銲墊（PAD）考量……………………44
4.3 輸入端與輸出端外部匹配考量……………………………….47
4.4 雙端輸出埠之非平衡考量…………………………………….48
4.5 三種增益模式模擬結果……………………………………….48
4.5.1 預計規格表……………………………………………....48
4.5.2 高增益模式（High Gain Mode）…………………………49
4.5.3 中增益模式（Medium Gain Mode）……………………51
4.5.4 低增益模式（Low Gain Mode）…………………………53
4.6 後端考量……………………………………………………….57
4.6.1 溫度偏移考量……………………………………………57
4.6.2 製程偏移考量……………………………………………58
4.6.3 鎊線與銲墊效應考量……………………………………60
4.7 量測環境考量………………………………………………….61
4.7.1 量測方式…………………………………………………62
4.7.2 散射係數（S parameter）量測方式……………………62
4.7.3 雜訊指數（Noise Figure）量測方式……………………63
4.7.4 輸入1dB增益壓縮點（IP1dB）量測方式………………63
4.7.5 輸入第三截止點（IIP3）量測方式………………………64
第五章 結論與未來展望
5.1 結論…………………………………………………………….65
5.2 未來展望……………………………………………………….66
參考文獻……………………………………………………………...67

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