[1]Henry Hendriks, Jim Crites, Gerald D’ Urso, Robert Fox, Thomas Lepkowski, and Bharat Patel, ”Challenges in Rapidly Scaling up Back-side Processing of GaAs Wafers”, Tyco Electronics, 2001, GaAs MANTECH, Inc.
[2]Craig P. Orlando, Joel L. Goodrich and Ernest L. Gosselin, “Backside Mounting Procedures for Semiconductor Wafer Processing”, Tyco Electronics, 2001, GaAs MANTECH, Inc.
[3]R. J. Olson, Jr., M. F. Taylor, R. J. Williams, T. S. Faska and M. Sundaram, “Alternate Backside Thinning of GaAs-Based Devices”, 1999 GaAs MANTECH, Inc.
[4]張瑞宗,“以厚膜光阻技術製備高縱橫比銅導柱之研究”交通大學材料科學研究所碩士論文,1999[5]J. M. West,”Electrodeposition and corrosion processes”,125~128
[6]C. H. Seah, S. Mridha, and L. H. Chan, “DC/Pulse Plating of Copper for Trench/Via Filling” J. Materials Processing Technol., 114, 233-239,141(2001)
[7]T. Kobaykhshy, J. Kawasaki, K.Mihara, T.Wamashita, and H.Honma, “Influence of Bath Composition to Via-Filling by Copper Electroplating” J. Japan Institute of Electronics, 3, 324-329,(2000).
[8]H. G. Creutz, R. M. Stevenson, and E. A. Romanowski, “Electrodeposition of Copper from Acid Baths”, U.S. Pat. 3,267,010,143(1966).
[9]陳宏澤 “界面活性劑在金屬脫脂及酸洗方面之應用”, 金屬表面技術雜誌,71,53 (1981)[10]李雅明,“固態電子學“,全華科技股份有限公司,264~269
[11]Dieter K. Schroder, ”Semiconductor Material and Device Characterization”, 2~5.
[12]田福助,”電化學基本原理與應用”,五洲出版社,(1999)
[13]萬海威,”多層印刷電路板之鍍銅製程”,電路板之訊雜誌7,24,(1988)
[14]方景禮,“電鍍添加劑總論”,表面技術雜誌,161,(1996)[15]S. C. Chang, J. M. Shieh, K. C. Lin, B. T. Dai, T. C. Wng, C. F. Chen, and M. S. Feng “Investigations of Effects of Bias Polarization and Chemical Parameters on Morphology and Filling Capability of 130 nm Damascene Electroplated Copper” J. Vac. Soc. Technol., 19,767-774, (2001).
[16]L. J. Turbini, J. A. Jachim, G. B. Freeman, and J. F. Lane, “Characterizing water soluble fluxes: Surface insulation resistance vs. electrochemical migration,” in 13th IEEE/CHMT Int. Electronics Manufacturing Technology Symp., 1992, pp. 80–84.
[17]Morton Antler, “Gold Plated Contacts: Effect of Thermal Aging on Contact Resistance” Contact Consultants, Inc. 821 Strawberry Hill Road East Columbus, 1997 IEEE.
[18]P.H. Lawyer and C.H. Fields, “Film Stress versus Plating Rate for Pulse-Plated Gold”2001 HRL Laboratories, LLC.
[19]Jeff L. Kersey, Jr., Life Member, IEEE, and Richard C. Blish, II, Senior Member, IEEE” Gold Dendrite Simulation: Root Cause Determination” IEEE Trans. on Electron Device, vol. 4, no. 2, June 2004.
[20]S.J. Huang, H.C. Chou, T.C. Lee, B. Lin, D.W. Tu, P.C. Chao, and C.S. Wu, “The Study of Dendrites Formation Mechanism to Enhance Gold Plating Process Yield, Throughput, and Solution Lifetime”, Tyco Electronics, 2003, GaAs MANTECH, Inc.
[21]S. Benhenda, N. Ben jemaa Associate Member, IEEE, and M. Bourir “Effect Of Pulse Plating Parameters On Electrical Contact Behavior Of Nickel Coatings”, PART A, vol. 17, no. 2, June 1994.