臺灣博碩士論文加值系統

近年來，隨著可攜式產品的蓬勃發展與商品生命周期不斷的縮短，廣泛使用於電子產品內部的唯讀記憶體（Read Only Memory，ROM）已經被一次寫入型記憶體（One Time Programmable Memory）所取代，使用熔絲（fuse）或反熔絲（anti-fuse）做為元件的一次寫入型記憶體在使用上比起唯讀記憶體更具有彈性。傳統上，熔絲以多晶矽熔絲（polysilicon fuse）及金屬熔絲（metal fuse）為主，編程（program）後熔絲的電阻值會上升，而反熔絲則是以電容器(capacitor)的形式製作，編程後反熔絲的電阻值會下降。由於熔絲與反熔絲在製造上並不符合現行的CMOS製程技術，製造成本較高，再加上編程時所需要的功率較大且耗時，使得一些以MOS元件做為反熔絲元件的技術相繼發表，再加上半導體製程技術的進步，所製造出來的一次寫入型記憶體具有低成本、高容量、編程速度快及資料保存時間長等優點。
使用MOS元件來製作反熔絲，其寫入的方法以閘極氧化層崩潰（Gate oxide breakdown）機制和穿透（punch through）機制為主，本研究利用n-MOSFET的閘極（Gate）-汲極（Drain）與閘極（Gate）-源極（Source）之間的氧化層崩潰，各形成一反熔絲元件，如此一來，便可以在單一MOS元件上儲存兩位元（bit）的資料，可以大幅提升一次寫入型記憶體的容量與密度，而且在製程上又可以符合標準CMOS製程技術。本研究將透過實驗的方式來驗證單一n-MOSFET元件製作2位元反熔絲裝置的可行性，確認寫入的資料可以清楚的辨識。

Recently, with the product development of portable product and shorten of product life, the Read Only Memory (ROM) often used inside of electric product has been replaced by One-Time-Programmable (OTP) Memory, and using OTP memory made by fuse or anti-fuse is more elastic than ROM. Traditionally, most of the fuse are polysilicon fuse and metal fuse. After programming, the fuse’s resistance will raise. The anti-fuse is performed by capacitor, and the resistance will reduce after program. Due to traditional fuse and anti-fuse are not compatible with CMOS process technology. More cost, also need more programming power and time. So that some technology which using MOS element for anti-fuse present one by one, additionally the advance of the technique of semiconductor, OTP memory owns low cost, high capacity, fast program time and good data retention.
The major ways which using MOS element to make anti-fuse are Gate oxide breakdown and punch through. Two anti-fuse elements present by using the Gate oxide breakdown of n-MOSFET between Gate-Drain and Gate-Source, so that two bits information can be programmed in single MOS element, and it can highly raise performance of OTP memory’s capacity and density. It’s compatible with CMOS process technology. This study will prove by testing that single n-MOSFET element makes 2 bits anti-fuse device, and confirming distinguished clearly after program anti-fuse.

Chapter 1 Overview of One-Time-Programmable Memories----------1
1.1 Memories in Microelectronic System Hierarchy-------------------1
1.2 Classification of the One-Time-Programmable Memories (OTPs)---3
1.3 Variety of Anti-fuses----------------------------------------------------5
1.4 Development Trend of Anti-fuse OTPs------------------------------7
1.5 Organizations of This Thesis------------------------------------------9
Chapter 2 High Field Breakdowns in MOSFETs------------------------10
2.1 Introduction------------------------------------------------------------10
2.2 Hot Carrier Injection--------------------------------------------------10
2.3 Band to Band Tunneling (BTBT)-----------------------------------12
2.4 Fowler-Nordheim (FN) Tunneling----------------------------------13
2.5 Punch Through---------------------------------------------------------15
2.6 Gate Oxide Breakdown-----------------------------------------------16
2.6.1 Thermo-chemical Model------------------------------------------18
2.6.2 AHI Model----------------------------------------------------------19
2.6.3 HR Model-----------------------------------------------------------20
Chapter 3 Characteristics of Anti-fuses----------------------------------22
3.1 Fabrication of Anti-fuse Devices------------------------------------22
3.2. Anti-Fuse Read / Program Operation------------------------------26
3.2.1 Initial State and Read Operation---------------------------------27
3.2.2 Program Operation-------------------------------------------------29
3.3 Characterization of Anti-fuses---------------------------------------30
3.4 Anti-fuse Device Simulation-----------------------------------------35
3.5 Discussion and Conclusion------------------------------------------ 38
Chapter 4 Conclusion and Future Prospective-------------------------41
4.1 Conclusion------------------------------------------------------------- 41
4.2 Future Prospective---------------------------------------------------- 41

Figure Caption
Fig 1-1: Memory table.
Fig 1-2: (a) Fuse function; (b) anti-fuse function.
Fig 1-3: The cross section of anti-fuse.
Fig 1-4: The cross section of poly-diffusion anti-fuse with an ONO dielectric.
Fig 1-5: The cross section of metal-metal anti-fuse.
Fig 2-1: Hot carrier junction.
Fig 2-2: Band diagram of hot carrier injection.
Fig 2-3: Band-to-band tunneling in a p-n junction.
Fig 2-4: Deep-depletion region is formed in gate to drain overlap region.
Fig 2-5: Band diagram of FN tunneling.
Fig 2-6: Band diagram of direct tunneling.
Fig 2-7: Schematic for punch through.
Fig 2-8: (a) Formation of traps in the gate oxide; (b) creation of conduction path through traps in the gate oxide..
Fig 2-9: (a) Increased traps in the gate oxide after conduction; (b) cross section of the gate oxide after hard breakdown.
Fig 2-10: (a) Chemical structure of SiO2; (b) oxygen vacancy in SiO2.
Fig 2-11: (a) Local electric field in SiO2; (b) the trap in SiO2.
Fig 2-12: SiO2 bond breakage due to hole current.
Fig 3-1: Wafer start.
Fig 3-2: Well implantation.
Fig 3-3: Gate oxide formation.
Fig 3-4: Define gate electrode.
Fig 3-5: Pocket implantation.
Fig 3-6: LDD implantation.
Fig 3-7: Spacer deposition and etch.
Fig 3-8: N+ source and drain implantation.
Fig 3-9: Source and drain anneal.
Fig 3-10: Salicide Ti deposition and etch.
Fig 3-11: One n-MOSFET can program two bits data.
Fig 3-12: (a) Bit-1 read condition: Vg=0, Vd=0~2, Vs=Vb=floating.
(b) Bit-2 read condition: Vg=0, Vs=0~2, Vd=Vb=floating.
Fig 3-13: Initial state current of n-MOSFET, Vs=Vb=floating.
Fig 3-14: (a) Bit-1 read condition: Vg=0, Vd=0~2, Vs=Vb=0.
(b) Bit-2 read condition: Vg=0, Vs=0~2, Vd=Vb=0.
Fig 3-15 Initial state current of n-MOSFET, Vs=Vb=0.
Fig 3-16: Bias circuit for gate oxide breakdown.
Fig 3-17 Programming I-V curves for gate oxide breakdown.
Fig 3-18: Step 1: programming bit-1 (n-MOSFET’s gate to drain region).
Fig 3-19: Step 3: programming bit-2 (n-MOSFET’s gate to source region).
Fig 3-20: Measurement current obtained after bit-1 is programmed.
Fig 3-21: Measurement current after bit-1 and bit-2 are programmed.
Fig 3-22: Measurement current obtained after bit-1 is programmed.
(read condition connect to ground)
Fig 3-23: Measurement current after bit-1 and bit-2 are programmed.
(read condition connect to ground)
Fig 3-24: The simulated the n-MOSFET cross section view.
Fig 3-25: The simulated ID-VG curves of n-MOSFET.
Fig 3-26: The simulated ID-VD curves of n-MOSFET.
Fig 3-27: The 2-D potential distribution of the anti-fuse programming bit-1.
Fig 3-28: The 2-D Field distribution of the anti-fuse programming bit-1.
Fig 3-29: After program bit-1 current path: (a) Id_bit-1; (b) Is_bit-2.
Fig 3-30: After program bit-2 current path: (a) Id_bit-1; (b) Is_bit-2.

Table Caption
Table 3-1: Anti-fuse program and read condition.
Table 3-2: Anti-fuse before and after programming.
Table 3-3: The process parameter for the Tsuperem-4 simulation.

[1-1] C. Y. Chang, S. M. Sze “ULSI Device”, pages 337.
[1-2] W. D. Brown, J. E. Brewer “Nonvolatile Semiconductor Memory Technology”, pages 1-2.
[1-3] A. Ohba, S. Ohbayashi “A7-ns 1-Mb BiCOMS ECL SRAM with Shift Redundancy”, IEEE Journal of Solid-State Circuit., vol 26, NO. 4, pages 507-512, Apr. 1991.
[1-4] D. W. Greve “Programming Mechanism on Polysilicon Resistor Fuses”, IEEE Journal of Solid-State Circuit., vol. SC-17, NO. 2, pages 349-354, Apr. 1982.
[1-5] C. D. Graaf “Novel high-density low cost diode programmable read only memory”, IDEM Technical Digest. pages 189-193, 1996.
[1-6] A. W. Longman “Application-Specific Integrated Circuits”.
[2-1] R. R. Troutman “VLSI limitations from drain induced barrier lowing”, IEEE Transaction of solid state circuits, pages 383-391, Apr. 1979.
[2-2] K. F. M. Mammy “Field-effect transistor for one-time programmable nonvolatile memory element” U. S. Patent 5834813, 1996.
[2-3] J. H. stathis. “Percolation models for gate oxide breakdown”, JJAP, pages 5757-5766, Nov. 1999.
[2-4] R. Degraeve, G. Groeseneken “ A consistent model for the thickness dependence of instrinsic breakdown in ultra-thin oxides”, IDEM, pages 863-866, 1995.
[2-5] C. Hu, Q. Lu “A unified gate oxide reliability model”, IEEE International Reliability Physics Symposium, pages 47-51, 1999.
[2-6] J. Sune, E. Wu “A new quantitative hydrogen-bases model for ultra-thin oxide breakdown” Symposium on VLSI Technology, pages 97-98, 2001.
[2-7] T. pompl, H. Wurzer “Investigation of ultra-thin gate oxide reliability behavior by separate characterization of soft breakdown and hard breakdown” IEEE international Reliability Physics Symposium, pages 40-47, 2000.
[2-8] C. T want “Hot carrier design for MOS devices and circuit”, 1992.
[2-9] F. Crupi, B. Kaczer “New insights into the relation between channel hot carrier degradation and oxide breakdown in short channel NMOSFETs” IEEE Electron Device Letters, pages 278-280, Apr. 2003.
[2-10] Y. Taur, T. H. Ning “Modern VLSI Device” pages 94-96, 1998.
[2-11] H. wong “Drain breakdown in submicron MOSFETs: a review” Microelectronics reliability, pages 3-14, Jul. 1999.
[2-12] H. Wong “Modeling of the parasitic transistor-induced drain breakdown in MOSFET’s” IEEE Transaction on Electron Devices, pages 2190-2196, December 1996.
[2-13] H. Wong “A physically-based MOS transistor avalanche breakdown model” IEEE Transaction on Electron Devices, pages 2197-2202, Dec. 1995.