臺灣博碩士論文加值系統

本論文針對局部應變矽與三維快閃記憶體兩方面來研究。在局部應變矽方面，為了能提升奈米尺寸的元件特性，由製程所引發的矽元件應變已被半導體工業所接受。這裡我們使用FLOOPS-ISE™和DESSIS-ISE™來模擬所提到的元件結構之製程與電性，其中新加坡大學於2004 IEDM發表於源極/汲極區使用矽碳(SiC)合金來增進50奈米場效N型電晶體的效能。對於NMOS而言，在源/汲極區域皆以矽碳合金(SiC)來當應力層，其電晶體通道上的應變強度與分佈視元件設計的參數而定，如：矽碳合金應力層間的距離、碳的莫耳百分比與應力層的深度都是主要的研究對象。我們可以經由理想的設計參數組合來得到一個遷移率與汲極電流均提升的理想電晶體。
在三維快閃記憶體方面，提出一個新型快閃記憶體結構來克服元件微縮上的問題，這些問題包含有在穿隧與多晶矽間介電層厚度的微縮、通道長度與電壓上的微縮。一個多重閘極的結構，可以改善元件的特性，如：次臨界擺幅與由汲極所引起的能障降低(DIBL)現象，都可以在不用考慮穿隧與多晶矽間介電層的厚度問題來達成。而垂直的結構可以克服通道的微縮問題。在此所提出的L型通道可以有效提升寫入的效率並且降低操作電壓。這裡使用DEVISE-ISE™和DESSIS-ISE™模擬其單一元件的結構與電性分析，並探討新型三維快閃記憶體與傳統快閃記憶體之間的差別。

This paper reports the local process stress on CMOS devices and develops a new three-dimension flash memory cell. Process-induced strained silicon device technology is being adopted by the semiconductor industry to enhance the performance of the devices in the nanometer realm. Both process and device simulations for the local process stress are simulated by FLOOPS-ISE™ and DESSIS-ISE™. The simulated process is similar to the 90 nm technology with a 50 nm gate length presented by NSU (National University of Singapore) in which a tensile strain is introduced in the NMOS channel using embedded SiC pockets in the source and drain areas. The strain field in the silicon channel of a metal–oxide–semiconductor transistor with silicon–carbon alloy source and drain stressors. The magnitude and distribution of the strain components, and their dependence on device design parameters such as the spacing between the silicon-carbon alloy stressors, the carbon mole fraction in the stressors and stressor depth were investigated. We can obtain an optimum combination of the above-mentioned device design parameters in terms of mobility enhancement, drain current enhancement.
Next, a novel flash memory cell was demonstrated to overcome the scaling issues. These issues including tunneling and inter-poly dielectrics thickness scaling, channel length scaling and voltage scaling. The multi-gate structure of propose cell can improve device character such as sub-threshold slope and drain induce barrier lowering (DIBL) without scaling tunneling and inter-poly dielectrics thickness. The vertical structure can overcome channel length scaling issue. The L channel can improve the program efficiency to reducing the operating voltage. The device structure and character was simulated by device simulator DEVISE-ISE™ and DESSIS-ISE™ simulation result showing the different from conventional and novel flash memory cell.

本文目次:
中文摘要 ....................................... Ⅰ
英文摘要 ....................................... Ⅲ
致謝............................................ V
目錄 ............................................VI
圖目 ..........................................VIII
表目 ......................................... XIII
第一章 導論 .................................... 1
1-1局部應變矽之背景 ............................ 1
1-2局部應變矽之研究動機與目的 .................. 2
1-3快閃記憶體之背景 ............................ 4
1-4快閃記憶體之研究動機與目的 .................. 5
第二章　理論基礎 ............................... 8
2-1 應變矽探討.................................. 8
2-1-1 應變與應力................................ 8
2-1-2 基本原理 ................................. 9
2-1-3 應變對能帶的影響 ......................... 15
2-2 局部應變矽元件介紹 ......................... 18
2-3熱載子注入之探討............................. 22
第三章　實驗步驟與方法 ......................... 28
3-1 局部應變矽場效電晶體模擬 ................... 28
3-2 快閃記憶體模擬 ............................. 34
第四章　結果與討論 ............................. 38
4-1局部應變矽場效電晶體模擬 .................... 38
4-1-1 使用氮化矽應力層來造成應變矽場效電晶體之模擬 ................................................ 38
4-1-2 使用矽鍺合金來造成應變矽P型場效電晶體之模擬 ................................................ 42
4-1-3 使用矽碳合金來造成應變矽N型場效電晶體之模擬 ................................................ 48
4-2新型快閃記憶體模擬 .......................... 56
4-2-1結構模擬 .................................. 56
4-2-2電性模擬 .................................. 59
第五章　結果與未來展望 ......................... 64
參考文獻........................................ 66

圖目次:
圖2-1 應力－應變關係圖.......................... 8
圖2-2 矽體受應變影響之示意圖(a)未受應變影響(b)受單軸壓縮(c)受雙軸壓縮(d)受單軸拉伸(e)受雙軸拉伸 ................................................ 10
圖2-3 矽鍺合金上成長矽會因製程條件的不同與晶格不匹配產生鬆弛矽或應變矽層.......................... 11
圖2-4 長晶時應變層厚度與鍺濃度之關係圖.......... 12
圖2-5 矽鍺合金百分比對其熔點關係................ 12
圖2-6 (a)由製程產生之3D應變分量................. 14
圖2-6 (b)應變效應對CMOS元件效能的影響........... 14
圖2-7 為(100)、(110)與(111)面，電子與電洞等位常數能量橢圓體切面圖.................................. 15
圖2-8 受雙軸拉伸應變與未受應變矽之改變(a)電子中之常數能量橢圓體 (b)價電帶(c)能帶結構圖............. 16
圖2-9 (a) Intel使用氮化矽應力層NMOS之穿透式電子顯微鏡圖............................................ 18
圖2-9 (b)Intel使用矽鍺合金PMOS之穿透式電子顯微鏡圖 ................................................ 18
圖2-10 使用矽碳合金NMOS之穿透式電子顯微鏡圖..... 20
圖2-11 (a)小源/汲極尺寸下對STI對通道之應力影響.. 21
圖2-11 (b)大源/汲極尺寸下對STI對通道之應力影響.. 21
圖2-11 (c)應力對電子載子遷移率之分佈圖.......... 21
圖2-11 (d)應力對電洞載子遷移率之分佈圖.......... 21
圖2-12將元件沿著通道方向分成三個部分之剖面圖.... 24
圖2-13新型元件通道之電流密度與位能分佈圖........ 25
圖2-14新型元件與傳統平面型元件之結構剖面圖...... 25
圖2-15幸運電子模型與Fiegna熱載子模型之I-V比較圖. 27
圖3-1 使用(a)氮化矽應力層與(b)在源/汲極區域填入矽鍺或矽碳合金來壓縮或拉伸矽通道，其簡易製程步驟.... 29
圖3-2 元件於座標與應力定義之說明圖.............. 30
圖3-3 快閃記憶體結構之製作方法的流程剖面示意圖.. 37
圖4-1 使用氮化矽應力層來造成應變矽場效電晶體模擬元件之掺雜濃度分佈................................ 39
圖4-2 使用氮化矽應力層來造成應變矽場效電晶體模擬元件之X方向應力分量分佈........................... 39
圖4-3 在X=0切線上對不同通道長度來觀察元件深度與X方向應變分量分佈關係.............................. 41
圖4-4 不同間隙壁寬度對矽通道區域X方向應變分量關係圖 ................................................ 41
圖4-5 (a)通道長度為45nm NMOS的Id-Vg曲線圖，考慮有無應變作用(b) 通道長度為45nm NMOS的Id-Vd曲線圖，考慮有無應變作用.................................... 42
圖4-6 使用矽鍺合金來造成應變矽P型場效電晶體之製程模擬元件之掺雜濃度分佈............................ 43
圖4-7 使用矽鍺合金來造成應變矽P型場效電晶體之製程模擬元件之X方向應力分量分佈....................... 43
圖4-8 為在X=0切線上對不同通道長度來觀察元件深度與X方向應變分量分佈關係 ........................... 45
圖4-9 合金百分比對應變分佈影響.................. 46
圖4-10 填入合金深度探討對應變分佈影響........... 46
圖4-11 通道長度對應變分佈影響................... 47
圖4-12 (a)通道長度為50nm PMOS的Id-Vg曲線圖，考慮有無應變作用(b) 通道長度為50nm PMOS的Id-Vd曲線圖，考慮有無應變作用.................................. 47
圖4-13改變結構對電洞遷移率增強比之影響分佈...... 48
圖4-14 使用矽碳合金來造成應變矽N型場效電晶體之製程模擬元件之掺雜濃度分佈.......................... 49
圖4-15 使用矽碳合金來造成應變矽N型場效電晶體之製程模擬元件之X方向應力分量分佈..................... 49
圖4-16 合金百分比對應變分佈影響................. 51
圖4-17 填入合金深度探討對應變分佈影響........... 51
圖4-18 通道長度對應變分佈影響................... 52
圖4-19 (a)通道長度為50nm NMOS的Id-Vg曲線圖，考慮有無應變作用(b) 通道長度為50nm NMOS的Id-Vd曲線圖，考慮有無應變作用.................................. 52
圖4-20不同碳莫耳百分比的飽和電流增益............ 54
圖4-21不同應力層深度下，飽和電流增益與常態化漏流圖
................................................ 55
圖4-22不同碳莫耳百分比與臨界電壓的關係圖........ 55
圖4-23快閃記憶體3D結構圖........................ 57
圖4-24快閃記憶體3D結構透視圖.................... 57
圖4-25快閃記憶體結構剖面圖...................... 58
圖4-26快閃記憶體結構佈局圖...................... 58
圖4-27快閃記憶體結構參數表...................... 59
圖4-28矽島狀區塊鳥瞰圖.......................... 60
圖4-29在不同矽島狀區塊厚度時的電流電壓特性...... 60
圖4-30在不同矽島狀區塊高度時的電流電壓特性...... 61
圖4-31在不同元件尺寸時的電流電壓特性............ 61
圖4-32在同元件尺寸為60奈米時的電流電壓特性...... 62
圖4-33低操作電壓下的程式化時間特性圖............ 63
圖4-34低操作電壓下的抹除時間特性圖.............. 63


表目次:
表1.1 近年國際各大廠及學術機構之相關研究........ 3
表2.1 Si3N4的沉積方式與特性..................... 19

[1] S. Thompson et al., IEDM Tech Dig., pp.61-64, (2002)
[2] T. Ghani et al., IEDM Tech Dig., pp.978-980, (2003)
[3] C.-H. Ge et al., IEDM Tech Dig., pp.73-76, (2003)
[4] F.-L. Yang et al., VLSI Symp, pp. 137-138, (2003)
[5] Z. Krivokapič et al., IEDM Tech Dig., pp.445-448, (2003)
[6] V. Chan et al., IEDM Tech Dig., pp.77-80, (2003)
[7] T. Sanuki et al., IEDM Tech Dig., pp.65-68, (2003)
[8] K. Oda et al., IEDM Tech Dig., pp.27-30, (2002)
[9] A. Shimizu et al., IEDM Tech Dig., pp.433-436, (2001)
[10] An Steegen et al., IEDM Tech Dig., pp.497-500, (1999)
[11] Kah Wee Ang, et al., “Enhanced Performance in 50 nm N-MOSFETs with Silicon-Carbon Source/Drain Regions,” IEDM, (2004)
[12] Yee-Chia Yeo, et al. “Strained Channel Transistor Using Strain Field Induced By Source and Drain Stressors, ” MRS, Vol.809 (2004)
[13] C. Gallon, et al. “Electrical analysis of external mechanical stress effects in short channel MOSFETs on (0 0 1) silicon ”, SSE, (2004)
[14] ISE TCAD Tools: DESSIS, FLOOPS-ISE User’s manual, ISE 10, (2004)
[15] 莊達人, VLSI 製造技術, pp.209, (1999)
[16] M. H. Lee, et al. “Comprehensive low-frequency and RF noise characteristics in strained-Si NMOSFETs”, IEDM Tech. Dig., pp. 69-72, (2003)

[17] M. H. Lee, et al. “The noise characteristics of strained-Si MOSFETs”, Int’l. SiGe Technol. and Dev. Meet. (ISTDM), 2004.
[18] S. Takagi, et al. “Device characterizations and physical models of strained-Si channel CMOS”, IEEE., pp.113-138, (2004)
[19] K. Mistry, et al. “Delaying forever: uniaxial strained silicon transistors in a 90nm CMOS technology”, Symp. on VLSI Tech. Dig., pp. 50-51, (2004)
[20] M. Burel, Electron. Lett. 37, 1201 (1995).
[21] F. Y. Huang, M. A. Chu, M. O. Tanner, and K. L. Wang, Appl. Phys. Lett., vol. 76, pp. 2680-2682, (2000)
[22] J. J. Welser, “The application of strained-silicon/relaxed-silicon germanium heterstructures to metal-oxide-semiconductor field-effect transistors ”, Stanford University (1994)
[23] J. L. Egley and D. Chidambarrao, “Strain Effects on Device Characteristics: Implementation in Drift-Diffusion Simulators,” Solid-State Electronics, vol. 36, no. 12, pp. 1653–1664, (1993.)
[24] G. L. Bir and G. E. Pikus, Symmetry and Strain-Induced Effects in Semiconductors, New York: John Wiley & Sons, (1974)
[25] Y. Kumagai et al., “Evaluation of change in drain current due to strain in 0.13-μm –node MOSFETs” SSDM, pp. 14-15, 2002
[26] 張家豪, “應變矽於奈米結構之分析與設計, ” 清華大學動力機械系碩士論文, (2004)
[27] C.S Smith,Phys.Rev.94,(1954)42.
[28] C.Herring, B.S.T.J.34(1955)237
[29] R.W.Keyes, Phys.Rev.103,(1956)1240
[30] 蔡宏聖, “應變工程在奈米尺寸CMOS元件製程之研究, ” 中原大學電子工程學系碩士論文, (2005)