臺灣博碩士論文加值系統

本論文提出一應用於多頻段壓控振盪器(VCO)之有系統的設計程序，並以一個涵蓋WCDMA和Bluetooth頻段之可調頻率範圍的VCO為範例。此範例電路採用串聯電容和切換式電容陣列來分別達到降低振盪器「增益」 (Kvco) 與切換不同頻段的目的，並由設計程序中所提出的公式快速計算出所需的串聯電容及陣列電容值。依此設計程序所得之VCO核心部份在1.8V電源電壓供應下的消耗功率為6.3mW，在1.86GHz載波頻率下所量測得到之1MHz頻率偏移的相位雜訊為-123.3dBc/Hz與2.40GHz載波頻率下所量測得到之3MHz頻率偏移的相位雜訊為-125.6dBc/Hz。此LC VCO晶片採用UMC 0.18 RF CMOS 製程技術製造。

This thesis presents a systematic design procedure of voltage-controlled oscillator (VCO) for multi-band application. A VCO that provides the tuning range covering WCDMA and Bluetooth applications is proposed as the demonstration example. Serial capacitors and switching capacitor-arrays have been adopted in the example circuit for the purpose of reducing “Kvco” and switching different frequency bands, respectively. The required values of serial capacitors and capacitor-arrays can be directly calculated according to the equations in the design procedure. The power consumption of VCO core is 6.3 mW through a 1.8V supply. The measured phase noise is –123.3dBc/Hz at 1MHz offset from the carrier frequency of 1.86GHz and –125.6dBc/Hz at 3MHz offset from the carrier frequency of 2.40GHz, respectively. The fully integrated LC VCO was fabricated in UMC 0.18 RF CMOS technology process.

目錄
摘要 Ⅰ
Abstract Ⅱ
圖目錄 Ⅵ
表目錄 Ⅸ
第一章 導論 1
1-1研究背景 1
1-2文獻回顧 3
1-3 研究目的及論文綱要 4
第二章 CMOS壓控振盪器原理架構 6
2-1 壓控振盪器原理分析 6
2-2 CMOS壓控振盪器架構 9
2-2-1環形振盪器 9
2-2-2 LC壓控振盪器 11
2-3相位雜訊 15
2-3-1相位雜訊模型 17
2-3-2相位雜訊對RF通訊系統的影響 22
第三章 CMOS壓控振盪器晶片設計程序 25
3-1 簡介 25
3-2設計程序步驟 26
3-3 模擬結果 32
第四章 CMOS壓控振盪器實作及量測結果 36
4-1製作與量測概況 36
4-2 模擬與量測結果比較 40
4-3 結果與討論 45
第五章 結論 47
參考文獻 48

圖目錄
圖1-1 (a) 藍芽應用(語音傳輸) 2
圖1-1 (b) 藍芽應用(資料傳輸) 3
圖2-1 正回授示意圖 7
圖2-2 振盪器負回授形式示意圖 7
圖2-3(a) 振盪訊號衰減 8
圖2-3(b) 穩定振盪 8
圖2-3(c) 主動元件提供負阻 8
圖2-4 振盪器之單埠負電阻等效電路 9
圖2-5 基本環形振盪器示意圖 10
圖2-6(a)理想電感電容並聯電路 12
圖2-6(b)實際電感與電容等效電路 12
圖2-6(c) RLC並聯等效電路 13
圖2-7 基本LC-tank振盪器示意圖 14
圖2-8 交連耦合對電晶體之小訊號模型 14
圖2-9 振盪器輸出頻譜 16
圖2-10 相位雜訊模型示意圖 18
圖2-11(a) 電流脈衝注入LC振盪器 19
圖2-11(b) 電流脈衝在最大振幅時注入 19
圖2-11(c) 電流脈衝在零交越時注入 20
圖2-12 相位雜訊形成示意圖 22
圖2-13 一般的RF收發機前端架構 23
圖2-14(a) 相位雜訊對接收機的影響 23
圖2-14(b) 相位雜訊對接收機的影響 24
圖2-15 相位雜訊對發射機的影響 24
圖3-1所提出的VCO之範例電路架構 26
圖3-2 電感對相位雜訊的貢獻值和對應之電感Q值的模擬結果 27
圖3-3 切換式電容陣列之電路結構 29
圖3-4 切換用的MOS電晶體之Wn與振盪器整體相位雜訊值的關係圖 29
圖3-5 偏壓電流與其對相位雜訊貢獻值的關係 30
圖3-6 差動對電晶體之外觀比與振盪器整體相位雜訊值的關係 31
圖3-7 多頻段LC VCO的佈局圖 32
圖3-8多頻段LC VCO輸出頻率與控制電壓模擬 33
圖3-9 VCO最高頻率之輸出功率模擬結果 33
圖3-10 VCO單端輸出波形模擬結果 34
圖3-11 載波頻率為1.92GHz的相位雜訊模擬結果 34
圖3-12 載波頻率為2.48GHz的相位雜訊模擬結果 35
圖4-1 壓控振盪器實體晶片照片 37
圖4-2 壓控振盪器測試電路板 37
圖4-3 On wafer量測示意圖及layout規格 39
圖4-4 On PCB量測方式示意圖 39
圖4-5 DC bias打線方式及GSG量測 39
圖4-6量測環境架設示意圖 41
圖4-7多頻段LC VCO輸出頻率與控制電壓關係圖 41
圖4-8 VCO輸出功率頻譜圖 42
圖4-9 1.868 GHz 量測之相位雜訊 42
圖4-10 2.4 GHz 量測之相位雜訊 43
圖4-11 VCO輸出波形時域圖 43

表目錄
表1-1行動通訊系統發展歷史 1
表1-2應用於WCDMA及Bluetooth之VCO的頻率及相位雜訊規格範圍 3
表1-3文獻上CMOS壓控振盪器效能比較表 4
表3-1各頻段頻率規格範圍及計算所得的Cs和Ca值 29
表3-2 VCO模擬結果的規格列表 35
表4-1多頻段壓控振盪器量測成果列表 44

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