臺灣博碩士論文加值系統

閘極接地的N型金氧半靜電放電保護元件在靜電放電情形下通常會遭遇發生電流不均勻分布的問題，本論文利用類三度空間的方式來分析此類行為。運用熱電模擬本文成功的重現出0.6微米製程下不同多晶矽指狀通道內不均勻放電電流分布情形，觀察通道下之電流濃度分佈以及載子分布為證據以說明通道開啟之現象，而N型金氧半靜電放電元件加入電阻耦合控制之後，經由模擬驗證可發現對於多指狀複晶矽通道的同步開啟有顯著的提升。耦合電阻值必須在15 KΩ以上以確保遭靜電放電時多指通道的均勻導通開啟。 除常用的閘極耦合方式之外，本論文更進一步提出一閘極-基極共同驅動方法，藉以改善傳統閘極耦合外接電阻值過大的缺點，實驗證實藉由此方式可有效降低閘極電阻值且從RC時間控制電路上的應用中可發現，此結構在耦合電容加大時可維持住閘極電壓，進而避免閘極電性過壓問題。

Gate-grounded NMOS ESD protection devices usually suffer from the non-uniform current distribution issue during ESD events. A quasi-three-dimensional simulation technique is applied to analyze such an ESD behavior. Using electrothermal simulation the nonuniform discharge current distribution on different poly-gate fingers is successfully reproduced in a 0.6 m CMOS technology. Resistance gate-coupled configuration of NMOS device is also simulated and demonstrates a significant improvement in homogeneous poly-gate multi-finger turn-on. The current density and carrier concentration distribution were observed as the evidence of channel turn-on phenomenon. The coupled resistance should be as large as 15 KΩ to insure its effect in simultaneous multi-finger triggering during ESD events. Besides the conventional gate-coupled method, a substrate and gate triggering technique is further proposed in this work to improve the drawback of the traditional gate coupled structure. Simulation result shows that the gate resistance can be receded significantly by substrate and gate triggered method and we also found in RC time control application, this structure can maintain the gate voltage to avoid the gate over driven effect.

Contents
Abstract（Chinese）…………………………………………………………………………... i
Abstract（English）…………………………………………………………………………… ii
誌謝………………………………………………………………………………………...... iii
Content………………………………………………………………………………………. iv
Table List………………………………………………………………………………...….. vi
Figure Captions…………………………………………………………………………….... vii
Chapter1 INTRODUCTION……………………………………………………………...…. 1
1.1 Background………………………………………………………………….... 1
1.2 The ESD Issues……………………………………………………………….. 2
　　　 1.3 Background of ESD Protection…………………………………………….…. 3
1.4 Thesis Organization……………………………………………………….….. 4
Chapter2 ESD STRESS MODELS, TEST STANDARDS, AND ESD PROTECTION
DEVICES………………………………………………………………………….
6
2.1 The ESD Models…………………………………………………………….... 6
2.1.1 Human Body Model（HBM）………………………………………….. 7
2.1.2 Machine Model（MM）………………………………………………… 8
2.1.3 Charged-Device Model（CDM）……………………………………… 9
2.1.4 Field-Induce Model（FIM）…………………………………………… 11
2.2 ESD Protection Devices…………………………………………………….… 12
2.2.1 Diffusion or poly resistor……………………………………………...... 12
2.2.2 P-N junction Diode…………………………………………………...… 14
2.2.3 Bipolar Junction Transistor……………………………………………... 16
2.2.4 MOS Transistor………………….…………………………………...… 19
Chapter 3 DESGIN AND ANALYSIS OF GATE COUPLED NMOS PROTECTION
DEVICE…………………………………………………………………………...
23
3.1 Motivation…..……………………………………………………………….... 24
3.2 Quasi Three Dimensional Simulation Scheme……………………………….. 29
3.3 Simulation Result and Analysis of Gate Coupled NMOS Device…………… 31
Chapter 4 DESGIN AND ANALYSIS OF SUBSTRATE AND GATE TRIGGERING
NMOS PROTECTION DEVICE……………………………………………..…..
43
4.1 Motivation……………………………………...……………….…………….. 43
4.2 Circuit Operation and Parameter Setting of Substrate and Gate Triggering
Scheme……………………………………………………………………...…
44
4.3 Design and Analysis of Substrate and Gate Triggering NMOS Device…….... 48
4.4 Potential Diagram Analysis……………………………………………….…... 55
4.5 Design and Analysis for RC Time Control Circuit………………………….... 58
Chapter 5 CONCLUSIONS……………………………………………………………......... 61
5.1 Conclusion……………………………………………………………………. 61
5.2 Future work……………………………………………………………….…... 62
Reference…………………………………………………………………………………..... 63
簡歷………………………………………………………………………………………...... 66

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