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研究生:林明彥
研究生(外文):Ming-yan Lin
論文名稱:實現在晶片上具學習能力之類神經模糊網路
論文名稱(外文):Implementation of Neural Fuzzy Networks with On-Chip Learning
指導教授:林正堅林正堅引用關係
指導教授(外文):Cheng-Jian Lin
學位類別:碩士
校院名稱:朝陽科技大學
系所名稱:資訊工程系碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:中文
論文頁數:66
中文關鍵詞:可程式化邏輯閘陣列類神經模糊網路倒傳遞演算法則同步干擾學習演算法遞迴式類神經模糊網路
外文關鍵詞:recurrent neural fuzzy networkbackpropagationsimultaneous perturbation methodField Programmable Gate Arrayneural fuzzy network
相關次數:
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  • 下載下載:66
  • 收藏至我的研究室書目清單書目收藏:0
可程式化邏輯閘陣列是近年來新興的一種硬體元件,它使硬體設計師能在短時間內將設計產品快速完成。類神經糢糊網路實現一般大多是以軟體的方式來模擬運算,但是利用軟體的模擬運算往往無法達到及時的需求。
在本論文中,將類神經模糊網路以硬體實現,硬體實現具有學習能力是很困難的問題,倒傳遞演算法則很常被拿來使用在類神經模糊網路,倒傳遞演算法則實現在硬體電路中是非常困難的,就網路中全部參數的修改量而言,則是一個複雜的運算電路。然而,我們利用同步干擾學習演算法硬體實現,同步干擾學習演算法只需要一個錯誤值修改網路的參數與倒傳遞演算法則不同。在高斯函數部分我們利用非線性函數轉換取代,減少硬體邏輯面積,則在類神經模糊網路缺點是他應用於內部前饋網路架構限制靜態問題,無法使用動態的問題,因此利用遞迴式類神經模糊網路方法解決動態問題,硬體實現遞迴式類神經模糊網路裡加入隨機存取記憶體,將網路全部的參數儲存在記憶體裡面,減少參數花費邏輯面積,我們確認設計的類神經模糊網路和遞迴式類神經模糊網路的能力,則透過實驗結果以獲得很好的結果。
Field Programmable Gate Array (FPGA) has become an emerging hardware device recently. It makes the hardware designer able to perform task in a short period of time. The implementation of neural fuzzy network (NFN) is usually simulated by the software, but the speed is not fast enough to reach the demand for real time.
In this thesis, neural fuzzy network is implemented by the hardware. The hardware implementation of NFN with learning ability is very difficult. Although the backpropagation (BP) learning algorithm is widely used in the NFN, it is still too complicated to be implemented in the hardware. However, we use the simultaneous perturbation method as a learning scheme of the implementation hardware. It is different from BP that simultaneous perturbation method uses only values of the error function for modifying quantities to all parameters. In order to reduce area of a chip, we utilize the traditional non-linear activation function to replace the Gaussian function.
A major disadvantage of existing NFN is that their application is limited to static mapping problems as a result of their internal feedforward network structure. Inefficiency occurs for temporal problems. Hence, a recurrent neural fuzzy network (RNFN) capable of solving temporal problems is needed.
The hardware implementation of RNFN adds to random access memory (RAM) which stores all parameters of network into RAM, reduces the parameters spending on the logic area. The major findings of the experiment show that the NFN and RNFN retaining good performance.
目錄
摘要 I
Abstract III
誌謝 V
目錄 VI
圖目錄 IX
表目錄 XI
第一章 簡介 1
1.1類神經模糊網路 1
1.2遞迴式類神經模糊網路 3
1.3可程式化邏輯閘陣列(FPGA)電路 4
1.4同步干擾學習演算法 5
1.5論文架構 6
第二章 類神經模糊網路系統架構介紹及學習演算法 7
2.1類神經模糊網路系統架構 7
2.2同步干擾學習演算法 11
第三章 類神經模糊網路硬體架構及模擬結果 14
3.1 FPGA硬體實現類神經模糊網路架構 14
3.1.1 硬體實現資料表示方式 16
3.1.2 高斯函數硬體實現 18
3.1.3 學習單元 22
3.1.4 參數修改單元 24
3.2 實驗結果 25
3.2.1 Exclusive OR學習 26
3.2.2 混亂訊號預測問題 28
第四章 遞迴式類神經模糊網路系統架構介紹及學習演算法 32
4.1遞迴式類神經模糊網路系統架構 32
4.2同步干擾學習演算法 36
第五章 遞迴式類神經模糊網路硬體架構及模擬結果 39
5.1 FPGA硬體實現遞迴式類神經模糊網路架構 39
5.1.1 隨機存取記憶體單元之控制方法 41
5.1.2高斯函數單元 43
5.1.3 記憶體學習單元 45
5.1.4 記憶體參數修改單元 48
5.2 實驗結果 49
5.2.1 時序預測問題 50
5.2.2 動態系統的識別 54
第六章 結論 59
參考文獻 61
個 人 簡 歷 66
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