臺灣博碩士論文加值系統

摘要

在此論文中主要介紹分析全數位鎖相迴路，在全數位鎖相迴路電路架構中，相位頻率偵測器的靈敏度及數位控制震盪器效能，決定整體全數位鎖相迴路的整體效能。在於現今的超大型積體電路的工業技術中，所強調的不只是電子產品有高的效能，最重要的縮短其生產製造的時間，所以運用標準電路原件達到自動化並縮短製造時間顯得更加重要，所提出的全數位鎖相迴路可以運用標準原件縮短製造時間。
在全數位鎖相迴路中數位控制震盪器，決定全數位鎖相迴路鎖定的時間以及輸出頻寬及頻率，本文中的全數位鎖相迴路具有更適合的延遲時間、更快的進行階段調整和更寬的鎖定範圍。
本論文完成高效能的數位控制振盪器及高靈敏度的頻率相位偵測器，縮短全數位鎖相迴路的設計時間及設計的複雜度，非常適合應用於系統晶片的運用。

Abstract

An all-digital phase-locked loop (ADPLL) circuit is presented. The feature of the ADPLL is that its resolution in the Phase and Frequency detector (PFD) and digitally controlled oscillator (DCO) exactly matches the gate-delay time. With the advances in deep-submicron technologies, the demand for high performance and short time-to-market integrated circuits has dramatically grown recently. The utilization of automated synthesis approach benefits from the standard cell-based design flow and hence implements a user-specified ADPLL within a short time.
A DCO is implemented for ADPLL applications. The DCO exactly matches the gate-delay time and is implemented with faster phase alignment and wider locking range using the same number of ring oscillator stages. Simulation results are presented to evaluate the performance of the DCO.
This paper presents a scheme to overcome the limitations of standard cells and to build up high resolution delay cell and high sensitivity PFD. Since both the design time and design complexity of the ADPLL is greatly reduced, the proposed scheme is very suitable for System-On-Chip (SOC) applications.

Contents

摘要 ix

Abstract ix

誌謝 (Acknowledgments) ix

Contents ix

List of Figures ix


Chapter 1 Introduction 1
1-1 Research Motivation 1
1-2 Thesis Outline 2

Chapter 2 Overview of A PLL 3
2-1 Analog Phase-Locked Loop (PLL) 3
2-2 Digital Phase-Locked Loop (DPLL) 7
2-3 All-Digital PLL (ADPLL) 10
2-4 Chapter Summary 11

Chapter 3 All-Digital Phase-locked loop (ADPLL) 12
3-1 ADPLL Design Issues 12
3-2 ADPLL Basic Block 13

Chapter 4 PFD Overview 14
4-1 Basic Concept 14
4-2 Finite-State Machine Analysis 16
4-3 PFD Circuit Design and Analysis 18
4-3.1 Phase Detector 18
4-3.2 Frequency Detector 20
4-4 Chapter Summary 21

Chapter 5 DCO Overview 21
5-1 Delay Cell Basic Circuit 21
5-1.1 AND-OR-INV Basic Circuit 22
5-1.2 OR-AND-INV Basic Circuit 22
5-2 Delay Line Circuit Overview 24
5-2.1 Delay Line Based Converter Architecture 24
5-2.2 Introduction to Digital Delay-Locked Loop 24
5-3 Introduction to Cycle -Controlled Delay Unit (CCDU) 26
5-3.1 Introduction to Hierarchical Delay Unit (HDU) 27
5-3.2 High Efficiency DCO Design Using CCDU and HDU 27
5-4 Chapter Summary 28

Chapter 6 System Simulation and Analysis 29
6-1 PFD Design and Analysis 29
6-1.1 PD Design and Analysis 29
6-1.2 FD Design and Analysis 30
6-1.3 PFD Design 31
6-2 DCO Design 32
6-2.1 CCDU Design 33
6-2.2 CDU Design 34
6-2.3 FDU Design 34
6-2.4 Control Unit Design 36
6-3 ADPLL System Design 37

Chapter 7 Conclusions 40

References

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