臺灣博碩士論文加值系統

本研究利用Verilog硬體描述語言(Hardware Description Language, HDL)和演算法狀態機制(Algorithmic State Machine, ASM)發展一個內嵌一階倒傳遞類神經網路(First-Order Backpropagation Neural Network)似MIPS架構之32位元精簡指令集處理器核心，進行行為模式設計，並配合SynaptiCAD模擬與Xilinx FPGA晶片軟體合成，最後並完成台積電0.18微米製程的超大型積體電路佈局設計。

This study develops a 32-bit RISC processor core embedded with first-order back-propagation neural network and MIPS-like architecture by using Verilog HDL and algorithmic state machine (ASM). The designed processor core is carried out through the behavioral stage by simulation of SynaptiCAD and synthesis of Xilinx FPGA development software. The VLSI layout of a neuro-microprocessor core is implemented under TSMC 0.18 um process technology at final.

封面內頁
簽名頁
授權書．．．．．．．．．．．．．．．．．．．．．．．．．iii
中文摘要．．．．．．．．．．．．．．．．．．．．．．．．iv
英文摘要．．．．．．．．．．．．．．．．．．．．．．．．v
誌謝．．．．．．．．．．．．．．．．．．．．．．．．．．vi
目錄．．．．．．．．．．．．．．．．．．．．．．．．．．vii
圖目錄．．．．．．．．．．．．．．．．．．．．．．．．．ix
表目錄．．．．．．．．．．．．．．．．．．．．．．．．．xi

第一章　緒論
1.1研究動機．．．．．．．．．．．．．．．．．．．．．．．1
1.2研究目的．．．．．．．．．．．．．．．．．．．．．．．2
第二章　微處理器
2.1基本要素．．．．．．．．．．．．．．．．．．．．．．．3
2.2精簡指令集電腦．．．．．．．．．．．．．．．．．．．．5
2.3MIPS CPU．．．．．．．．．．．．．．．．．．．．．．．6
2.4MIPS指令表示法．．．．．．．．．．．．．．．．．．．．8
2.5演算法狀態機．．．．．．．．．．．．．．．．．．．．．11
第三章 類神經網路
3.1類神經網路簡介．．．．．．．．．．．．．．．．．．．．14
3.2類神經網路神經元構造及數學模型．．．．．．．．．．．．15
3.3倒傳遞類神經網路的運作．．．．．．．．．．．．．．．．19
3.4倒傳遞類神經網路公式推導．．．．．．．．．．．．．．．21
3.5類神經網路應用層面介紹．．．．．．．．．．．．．．．．24
第四章 結果與討論
4.1似MIPS CPU程式轉換．．．．．．．．．．．．．．．．．．26
4.2浮點數運算、自然指數運算單元．．．．．．．．．．．．．30
4.3類神經網路測試範例以及結果．．．．．．．．．．．．．．37
4.4Neuro-Microprocessor．．．．．．．．．．．．．．．．．43
4.5Cadence積體電路佈局．．．．．．．．．．．．．．．．．．44
第五章 結論與建議．．．．．．．．．．．．．．．．．．．．．52
參考文獻．．．．．．．．．．．．．．．．．．．．．．．．54
附錄．．．．．．．．．．．．．．．．．．．．．．．．．．57

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