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研究生:鄭凱仁
研究生(外文):Cheng Kai Jen
論文名稱:CMOS元件ESD保護電路可靠性之研究
論文名稱(外文):ESD Implantationsin in Sub-Quarter-Micron Bulk CMOS Technology
指導教授:鍾翼能鍾翼能引用關係
指導教授(外文):Yi-Nung Chung
學位類別:碩士
校院名稱:大葉大學
系所名稱:電機工程學系碩士在職專班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:中文
論文頁數:45
中文關鍵詞:already-on (native)元件NMOS靜電放電
外文關鍵詞:already-on (native) componentNMOSESD
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在奈米CMOS 積體電路中,靜電放電(ESD)防護能力隨著元件的尺寸縮減而大幅地降低,傳統的ESD 防護電路設計及方法已不堪使用,所以在奈米製程中ESD防護元件的挑選及ESD 防護電路設計必需更加以改良。我們針對一個具有初始導通特性already-on (native)的NMOS 元件,研究其ESD 元件特性,並提出其在奈米CMOS 積體電路上的創新應用。這種already-on (native)NMOS 元件具有較低或是負臨界電壓(threshold voltage)的特性。當IC 受到ESD轟擊時,這種already-on (native)元件會具有初始導通的特性,也就是說,當IC浮接時,這種already-on (native)元件就會在導通狀態下來等待ESD 的轟擊。所以這種already-on (native)元件在理論上具有最快的導通速度及最低的觸發電壓。如此,才能有效率地保護在奈米製程中超薄的閘極氧化層(厚度小於15Å)。IC 在一般正常操作下,為了使這種already-on (native)元件關閉來避免不必要的漏電流,該元件的閘極需要加上一負偏壓來關閉元件的通道。
In enduring the nano CMOS integrated circuit, the static discharges (ESD) the protective capacities are reduced by a wide margin as the size of the component is reduced , traditional ESD already to protect circuit design and method can't bear using, endure nano system ESD protect component select and ESD protect circuit it designs to be must in order to improve. We have initial NMOS component which lead open characteristic already-on (native ) to one, study its ESD component characteristic, and propose its innovative application in enduring the rice CMOS integrated circuit. This kind of already-on (native ) NMOS component has characteristic lower or of shouldering the critical voltage (threshold voltage more ). When IC is shelled by ESD, this kind of already-on (native ) component will lead the open characteristic initially , that is to say, when IC floats and connects , this kind of already-on (native ) component will be leading the open state and coming down to wait for the bombardment of ESD. So this kind of already-on (native ) component has leading the open speed and the lowest voltage of touching off fast most in theory . Like this , could protect in endure metric system ultrathin Gate Oxide layer in the Cheng efficient (thickness is smaller than 15Å). IC is under the general normal running , in order to make this kind of already-on (native ) component shut off and avoid unnecessary leaking the electric current, the bar of this component needs to add the passway where the bias voltage of a loss shut off the component .
封面內頁
簽名頁
授權書..........................iii
中文摘要.........................iv
英文摘要.........................v
誌謝...........................vi
目錄...........................vii
圖目錄..........................ix
表目錄.........................xi

第一章 諸論
1.1 研究動機....................1
1.2研究目的.....................1
1.3論文架構.....................3
第二章 靜電放電防護設計之基本概念
2.1靜電放電的產生..................4
2.2 靜電放電模型.................. 4
2.2.1 人體放電模式...............5
2.2.2 機器放電模式...............7
2.2.3 元件充電模式...............8
2.2.4 電場感應模式...............10
2.3防護電路概念..................11
2.3.1 防護電路之設計概念............12
2.4防護元件之選用...............16
2.5靜電放電防護電路的實例.............19
第三章 靜電放電主要放電路徑及數學模型
3.1 靜電放電至電感、電容、電阻的簡單模型 .....22
3.2 CR-R 放電模型..................23
3.2.1 暫態分析.................23
3.2.2能量分析.................24
3.3 CR-C 放電模型..................25
3.3.1暫態分析.................26
3.3.2穩態分析.................27
3.3.3耦和雜訊分析...............27
3.3.4能量分析.................28
3.4 CR-L 放電模...................29
第四章 CMOS靜電放電防護元件
4.1 簡介......................31
4.2元件及其特性分析.................32
4.3 Already-on (native)元件的DC 特性........33
4.4 TLP(Transmission Line Pulsing) .........35
4.5元件的ESD 保護單元...............39
4.6全晶片ESD 防護設計................41
4.7 具有複晶矽二極體的負電壓產生電路........43
第五章 結論與展望....................46
參考文獻.........................47


圖目錄

圖2.1人體放電模式靜電放電電流與時間關係........6
圖2.2人體放電模式等效圖................6
圖2.3機器放電模式等效圖................7
圖2.4元件充電放電模式等效圖..............9
圖2.5人體放電模式(2KV) 、機器放電模式(200V)和元件充電模式(1KV)放電電流與時間比較圖............10
圖2.6 全方位靜電放電防護電路..............13
圖2.7異常靜電放電損傷積體電路內部電路的示意圖.....15
圖2.8各種ESD防護元件的I-V特性............18
圖2.9 CMOS積體電路中幾種常見的輸入級ESD防護電路...20
圖3.1 CR-R 模型....................23
圖3.2 CR-R 放電之負載電壓波形.............24
圖3.3 CR-C 放電模型..................26
圖3.4 CR-C 放電之負載電壓電流波形...........27
圖3.5 CR-L 模型....................29
圖4.1 (a)一般元件的詳細結構圖,(b)already-on (native)元件的詳細結構圖......................32
圖4.2 (a)一般元件的詳細結構圖,(b)already-on (native)元件的詳細結構圖......................33
圖4.3 Already-on (native)元件的DC 的特性曲線圖......35
圖4.4 Already-on 元件與一般元件的TLP 特性曲線圖....36
圖4.5 Already-on 元件與一般元件的觸發電壓Vt1 與穩態電壓Vh 在不同通道長度下的比較..............38
圖4.6 Already-on (native)元件與一般元件的二次崩潰電流It2 與導通電阻Ron 在不同通道長度下的比較.........39
圖4.7 ESD 防護單元由(a)單一already-on (native)元件構成, (b)一個already-on(native)及一個FOD 元件所組成....40
圖4.8單一FOD 元件與already-on 元件結合FOD 元件單元的TLP 特性圖......................41
圖4.9利用具有起始導通特性之ESD 防護單元所形成的全晶片ESD 防護電路...................43
圖4.10利用複晶矽二極體所構成的負電壓產生電路的電路圖..44
圖4.11負電壓產生電路在輸入方波後所產生的負電壓值....45


表目錄

表2.1 人體放電模式(HBM)工業標準及耐壓能力表......7
表2.2 機器放電模式(MM)工業標準及耐壓能力表.......8
表2.3 元件充電放電模式(CDM)工業標準及耐壓能力表....9
表2.4 靜電放電規範與防治方法..............11
表2.5 CMOS積體電路晶片上靜電放電防護電路的設計考量..14
表2.6 各種元件在0.8微米CMOS製程下ESD耐壓能力之比較21
1.MIL-STD-883C method 3015.7, "Military Standard Test Methods and Proc. For Microelectronics", Dept. of Defense, Washington, D. C., U.S.A., 1989.
2.ilding-in ESD/EOS reliability for Sub-Halfmicron CMOS Processes," IEEE Transactions on Electron Devices, Vol. 43, No. 6, pp. 991-999, June 1996.
3.Ming-Dou Ker and Tain-Shun Wu, "ESD Protection for Submicron CMOS IC’s—A Tutorial,” CCL Technical Journal, Vol. 42, pp. 10-24, Sept. 1995
4.T. J. Maloney and N. Khurana, "Transmission Line Plising Techniques for Circuit Modeling of ESD Phenomena, " EOS/ESD Symposium Proceedings, EOS-7, pp. 49-54, 1985.
5.C. Duvvury, R. N. Rountree, and O. Adams, "Internal chip ESD phenomena beyond the protection circuit," IEEE Trans. on Electron Devices, vol. 35, pp.2133-2139, Dec., 1988.
6.M. D. Jaffe and P. E. Cottrell, "Electrostatic discharge protection in a 4-Mbit DRAM," EOS/ESD Symp. Proc., 1990, EOS-12, pp.218-223.
7.C. C. Johnson, T. J. Maloney, and S. Qawami, "Two unusual HBM ESD failure mechanisms on a mature CMOS process," EOS/ESD failure mechanisms on a mature CMOS process," EOS/ESD Symp. Proc., 1993, EOS-15, pp.225-231.
8.H. Terletzki, W. Nikutta, and W. Reczek, "Influence of the series resistance of on-chip power supply buses on internal device failure after ESD stress," IEEE Trans. on Electron Devices, vol. 40, pp. 2081-2083, Nov., 1993.
9.C.-N. Wu, M.-D. Ker, et al., "Unexpected ESD damage on internal circuits of sub-μm CMOS technology," Proc. of International Electron Devices and Materials Symposium, 1996, pp.143-146.
10.EOS/ESD Standard for ESD Sensitivity Testing, EOS/ESD Association, NY., 1993.
11.C. Duvvury and C. Diaz., “Dynamic gate coupling of NMOS for efficient output
12.ESD protection,” in Proc. of IRPS, 1992, pp.141-150.
13. M.-D. Ker, C.-Y. Wu, T. Cheng, and H.-H. Chang, “Capacitor-couple ESD
14.protection circuit for deep-submicron low-volage CMOS ASIC,” IEEE Trans. on
15.VLSI Systems, vol. 4, no. 3, pp. 307-321, 1996.
16. M.-D. Ker, T.-Y. Chen, and C.-Y. Wu., “Design of cost-efficient ESD clamp
17.circuits for the power rails of CMOS ASIC’s with substrate-triggering technique,”
18.in Proc. of IEEE Int. ASIC Conf. and Exhibit, 1997, pp. 287-290.
19.M.-D. Ker, T.-Y. Chen, C.-Y. Wu, H. Tang, K.-C. Su, and S.-W. Sun, “Novel
20.input ESD protection circuit with substrate-triggering technique in a 0.25-μm
21.shallow-trench-isolation CMOS technology,” in Proc. of IEEE Int. Symp. on
22.Circuits and Systems, 1998, vol. 2, pp. 212-215.
23.C. Duvvury, S. Ramaswamy, A. Amerasekera, R. Cline, B. Anderson, and V.
24.Gupta., “Substrate pump NMOS for ESD protection applications,” in Proc. of
25.EOS/ESD Symp., 2000, pp. 7-17.
26. M.-D Ker, T.-Y. Chen, and C.-Y. Wu, “ESD protection design in a 0.18-μm
27.silicide CMOS technology by using substrate-triggered technique,” in Proc. of
28.IEEE Int. Symp. on Circuits and Systems, 2001, pp.754-757.
29. M.-D. Ker, C.-Y. Chang, and H.-C. Jiang, “Design of negative charge pump
30.circuit with polysilicon diodes in a 0.25-μm CMOS process,” in Proc. of IEEE
31.AP-ASIC Conf., 2002, pp. 145-148.
32. M.-D Ker, T.-Y. Chen, and C.-Y. Chang, “ESD protection design for CMOS RF
33.integrated circuits,” in Proc. of EOS/ESD Symp., 2001, pp. 346-354.
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