臺灣博碩士論文加值系統

本論文設計一個低功率的2-1 MASH 三角積分調變器(2-1 MASH Delta-Sigma Modulator),可應用於聲頻應用上,此調變電路接上Decimator Filter即可組成完整的類比數位轉換器。為了可攜帶性的考量,電池的選取對於可攜帶性產品是很重要的,此調變器使用單端電源3.3V,消耗功率約160mW。本調變器使用全差動交換式電容電路(Switched-capacitor)的電路來實現,信號頻率為93.75KHz,超取樣頻率為64時,所得到的SNR值為76dB,解析度為12-bit,使用的製程為TSMC 0.18um 1P6M的RF Mixed mode 製程。

This paper presents a low-power 2-1 MASH Delta-Sigma modulator,which can be use for vice application.We can connect a decimator filter to be a complete A/D converter.The choice of battery is an important issue for protability products.The modulator use the signle power supply (3.3V).The power dissipation of the modulator is about 160mW.The modulator is implemented with switched-capacitor technique,the signal frequency is 92KHz,the OSR is 64,the SNR is 76dB,and the resolution is about 12-bit.The modulator is implemented in the TSMC 0.18um 1P6M RF Mixed mode process.

Page
ABSTRACT(IN CHINESE) .......................................I
ABSTRACT(IN ENGLISH).......................................II
CONTENTS ..................................................IV
LIST OF FIGURES...........................................VII
LIST OF TABLES .............................................X
CHAPTER 1
INTRODUCTION ...............................................1
1.1 Motivation .............................................1
1.2 Oversampling A/D Converters .....................1
1.3 First-Order Sigma-Delta A/D Converters ..........1
1.4 Second-Order Sigma-Delta A/D Converters ..........3
1.5 Multi-Stage Noise Shaping (MASH) Sigma-Delta A/D
Converters .......................................3
1.5.1 2-1 MASH Sigma-Delta A/D Converters .......4
1.6 Summary...........................................5
CHAPTER 2
System Design...............................................7
2.1 ADC Architecture .................................7
2.1.1 Second-Order Sigma-Delta Architecture .....8
2.1.2 2-1 MASH Sigma-Delta Architecture .....9
2.2 Simulink Models of Sigma-Delta ADCs ..............9
2.2.1 Dynamic Range ............................10
2.2.2 DC Tones and Dithering ...................11
2.2.3 Power Consumption ........................14
2.3 Signal Scaling ..................................15
2.4 Thermal Noise ...................................16
2.5 Effect of Circuit Noise .........................18
2.6 Amplifier DC Gain ...............................20
2.7 Amplifier Settling ..............................22
2.8 Conclusion ......................................23
CHAPTER 3
Circuit Implementation.....................................24
3.1 First Integrator ................................24
3.2 Second Integrator ...............................27
3.3 Third Integrator ................................28
3.4 Operational Trans-conductance Amplifiers (OTAs)..31
3.5 Common mode feedback (CMFB) .....................32
3.6 Comparators .....................................33
3.7 Latches and DACs ................................34
3.8 Clock Generation ................................35
3.9 Conclusion.......................................37
CHAPTER 4
Simulation of System Circuit..............................38
4.1 Clcok Generator .................................38
4.2 Folded cascode OTA with gain boosting fully-differential
Amplifer....... .................................39
4.3 Regenerative comparator Simulation .................42
4.4 Wide-Swing Constant-Transconductance Simulation.....44
4.5 Conclusion..........................................46
CHAPTER 5
Summary....................................................48
References.................................................49

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