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[1]S. M. Sze, Physics of Semiconductor Devices, Wiley-Interscience, New York 1981. [2]S. M. Sze, Semiconductor devices, physics and technology, Wiley, New York, 2002. [3]S. M. Sze, Microelectronics Technology: Challenges in the 21st Century in: S. Luryi, J. Xu, and A. Zaslavsky (Eds), Future Trends in Microelectronics, Wiley-IEEE, 2002, pp. 3-16. [4]C. Y. Chang and S. M. Sze, ULSI devices, John Wiley & Sons, New York, 2000. [5]Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, New York, 1998. [6]T.-S. Chao, Y.-H. Lin, and W.-L. Yang, ” Mobility Enhancement of MOSFETs on p-Silicon (111) With In situ HF-Vapor Pre-Gate Oxide Cleaning”, IEEE Electron Devices Letters, vol. 25, no. 9, pp. 625-627, 2004. [7]W.-L. Yang, T.-S. Chao and K.-H. Lai, ”Suppression of Boron Penetration in P+-Poly-SiGe Gate P-Channel Metal-Oxide-Semiconductor Field-Effect Transistor Using NH3-Nitrided and N2O-Grown Gate Oxides”, Jpn Journal of Applied Physics, vol. 43, no. 11A, pp. 7462-7463, 2004. [8]C. Fenouillet-Beranger, T. Skotnicki, S. Monfray, N. Carriere, and F. Boeuf, “Requirements for ultra-thin-film devices and new materials for the CMOS roadmap,” Solid-State Elec. Vol. 48, No. 6, June 2004, pp. 961-967. [9]B.-Y. Nguyen et al., “Integration challenges of new materials and device architectures for IC applications,” Proc. Int. Integrated Circuit Design and Technology Conf., May 17–20, 2004, pp. 237–243. [10]S.Watanabe, “Impact of three-dimensional transistor on the pattern area reduction for ULSI,” IEEE Trans. Electron Devices, vol. 50, no. 10, pp. 2073–2080, Oct. 2003. [11]S. Monfray et al., “50 nm-gate all around (GAA)-silicon on nothing (SON)-devices: A simple way to co-integration of GAA transistors within bulk MOSFET process,” Digest of Technical Papers of The 2002 Symposium on VLSI Technology, Jun. 11–13, 2002, pp. 108–109. [12]J. P. Colinge, M. H. Gao, A. Romano-Rodriguez, H. Maes, and C. Claeys, “Silicon-on-insulator ‘gate-all-around device’,” Technical Digest of International Electron Devices Meeting (IEDM), Dec. 9–12, 1990, pp. 595–598. [13]J.-P. Colinge, “Multiple gate SOI MOSFETs,” Solid State Electron., vol. 48, no. 6, pp. 897–905, Jun. 2004. [14]J. A. Choi, K. Lee, Y. S. Jin, Y. J. Lee, S. Y. Lee, G. U. Leet, S. H. Lee, M. C. Sun, D. C. Kimt, Y. M. Lee, S. G. Bae, J. H. Yang, S. Maeda, N. I. Lee, H. K. Kang, K. P. Suh, “Large Scale Integration and Reliability Consideration of Triple Gate Transistors,” Technical Digest of International Electron Devices Meeting (IEDM), 2004, pp. 647-650. [15]F.-L. Yang, D.-H. Lee, H.-Y. Chen, C.-Y. Chang, S.-D. Liu, C.-C. Huang, T.-X. Chung, H.-W. Chen, C.-C. Huang, Y.-Chia Y., Y. Li, J.-W. Lee, and P. Chen, M.-S. Liang, and C. Hu, “5nm-Gate Nanowire FinFET,” Digest of Technical Papers of The 2004 Symposium on VLSI Technology, Honolulu, Hawaii, USA, June 15-19, 2004, pp. 196-197. [16]F.-L. Yang, H.-Y. Chen, F.-C. Chen, C.-C. Huang, C.-Y. Chang, H.-K. Chiu, C.-C. Lee, C.-C. Chen, H.-T. Huang, C.-J. Chen, H.-J. Tao, Y.-C. Yeo, M.-S. Liang, C. Hu, “25 nm CMOS Omega FETs,” Technical Digest of International Electron Devices Meeting (IEDM), 2002, pp. 255-258. [17]S. Xiong and J. Bokor, “Sensitivity of double-gate and FinFET devices to process variations,” IEEE Trans. Electron Devices, vol. 50, no. 11, pp. 2255–2261, Nov. 2003. [18]T. Schulz, W. Rosner, E. Landgraf, L. Risch, and U. Langmann, “Planar and vertical double gate concepts”, Solid-State Elec., vol. 46, no. 7, pp. 985-989, July 2002. [19]H. Wakabayashi, S. Yamagami, N. Ikezawa, A. Ogura, M. Narihiro, K. Arai, Y. Ochiai, K. Takeuchi, T. Yamamoto, and T. Mogami, “Sub-10-nm planar-bulk-CMOS Devices using lateral junction control”, Technical Digest of International Electron Devices Meeting (IEDM), 7-10 Dec. 2003, pp. 20.7.1-20.7.3. [20]S. Zhang, X. Lin, R. Huang, R. Han, and M. Chan, “A self-aligned, electrically separable double-gate mos transistor technology for dynamic threshold voltage application”, IEEE Transactions on Electron Devices, vol. 50, no. 11, pp. 2297-2300, Nov. 2003. [21]X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, “Sub 50-nm FinFET: PMOS”, Technical Digest of International Electron Devices Meeting (IEDM), 5-8 Dec. 1999, pp. 67-70. [22]J. P. Colinge, M. H. Gao, A. Romano-Rodriguez, H. Maes, and C. Claeys, “Silicon-on-insulator gate-all-around device,” Technical Digest of International Electron Devices Meeting (IEDM), 1990, pp. 595-598. [23]H. Takato, K. Sunouchi, N. Okabe, A. Nitayama, K. Hieda, F. Horiguchi, and F. Masuoka, “Impact of surrounding gate transistor (SGT) for ultra-high-density LSI’s,” IEEE Trans. Elec. Devices, pp. 573-578, 1991. [24]D. M. Fried, E. J. Nowak, J. KeIdzierski, J. S. Duster, and K. T. Komegay, “A fin-type independent-double-gate NFET”, Proceedings of the 2003 Device Research Conference, June 23-25, 2003, pp. 45-46 . [25]B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Ho, Q. Xiang, T.-J. King, J. Bokor, C. Hu, M.-R. Lin, and D. Kyser, “FinFET scaling to 10 nm gate length,” Technical Digest of International Electron Devices Meeting (IEDM), Dec. 2002, pp. 251 -254. [26]M. J. Gilbert and D. K. Ferry, “Efficient quantum three-dimensional modeling of fully depleted ballistic silicon-on-insulator metal–oxide–semiconductor field-effect-transistors,” J. Appl. Phys., vol. 95, no. 12, pp. 7954–7960, Jun. 2004. [27]S. N. Balaban, E. P. Pokatilov, V. M. Fomin, V. N. Gladilin, J. T. Devreese, W. Magnus, W. Schoenmaker, M. Van Rossum, B. Sorée, “Quantum transport in a cylindrical sub-0.1mm silicon-based MOSFET,” Solid-State Elec., Vol. 46, No. 3, pp. 435-444, March 2002. [28]N. Sano, A. Hiroki, and K. Matsuzawa, “Device modeling and simulations toward sub-10 nm semiconductor devices”, IEEE Trans. Nanotech., Vol. 1, No. 1, pp. 63-71, Dec. 2002. [29]T. J. Walls, V. A. Sverdlov, and K. K. Likharev, “MOSFETs below 10 nm: quantum theory”, Physica E, vol. 19, no. 1-2, pp. 23-27, July 2003. [30]D. K. Ferry, “The onset of quantization in ultra-submicron semiconductor devices,” Superlattices and Microstructures, Vol. 27, No. 2/3, pp. 61-66, Feb. 2000. [31]R. Venugopal, Z. Ren, S. Datta, M. S. Lundstrom, and D. Jovanovic, “Simulating quantum transport in nanoscale transistors: Real versus mode-space approaches”, J. Applied Physics, Vol. 92, No. 7, pp. 3730-3739, Oct. 2002. [32]J. R. Watling, A. R. Brown, A. Asenov, A. Svizhenko, and M. P. Anantram, “Simulation of direct source-to-drain tunnelling using the density gradient formalism: Non-Equilibrium Greens Function calibration”, Proc. IEEE Int. Conf. Simulation of Semiconductor Processes and Devices (IEEE SISPAD), 4-6 Sep. 2002 pp. 267 -270. [33]J. R. Watling, A. R. Brown, and A. Asenov, “Can the Density Gradient Approach Describe the Source-Drain Tunnelling in Decanano Double-Gate MOSFETs?”, J. Comput. Elec., Vol. 1, No. 1-2, pp. 289-293, July 2002. [34]M. G. Ancona, “Equations of state for silicon inversion layers”, IEEE Trans. Elec. Dev., Vol. 47, No. 7, pp. 1449-1456, July 2000. [35]M. G. Ancona, Z. Yu, R. W. Dutton, and P. J. Vande Voorde, “Density-gradient analysis of MOS tunneling”, IEEE Trans. Elec. Dev., Vol. 47, No. 12, pp. 2310-2319, Dec. 2000. [36]A. Schenk and A. Wettstein, “2D Analysis of Source-to-Drain Tunneling in Decananometer MOSFETs with the Density-Gradient Model,” Tech. Proc. Modeling and Simulation of Microsystem, 2002, pp. 552-555.
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