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研究生:李義成
研究生(外文):Yi-chen Lee
論文名稱:場效應電晶體不同閘極結構與通道長度之模擬與比較
論文名稱(外文):Simulation and Comparison of MOSFETs with Different Gate Structure and Channel Length
指導教授:楊文祿
學位類別:碩士
校院名稱:逢甲大學
系所名稱:資訊電機工程碩士在職專班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:中文
論文頁數:68
中文關鍵詞:場效應電晶體閘極結構與通道長度
外文關鍵詞:Channel LengthMOSFETsGate Structure
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金屬氧化物半導體場效應電晶體技術的發展在微電子工業,尤其是積體電路的設計與消費性產品應用上扮演十分重要的角色;為了做出電特性更好更穩定的電晶體,以矽材料為主的單閘極金屬氧化物半導體場效應電晶體於過去四、五十年來已被成功發展。電晶體通道由早期的微米級縮小進入深次微米乃至於近來奈米等級時,新材料、新製程與新結構的研究已引起廣泛的興趣。新結構電晶體有其優點與特性也形成一個有趣的研究方向。
本論文研究通道長度小於32奈米的矽金屬氧化物半導體場效應電晶體在不同閘極結構下的元件特性。論文中探討奈米級單閘極、雙閘極、三閘極以及圓形全閘極矽金屬氧化物半導體場效應電晶體的基本電特性。透過三維度電腦模擬,求解具有量子效應的傳輸方程組(也就是泊松方程式、載子流連續方程式以及密度梯度方程式),論文中比較了各種電晶體的導通電流、截止電流、臨界電壓、短通道特性等。研究發現,在相同的元件參數設定下,針對上面關心的電特性,矽圓形全閘極電晶體在四種電晶體結構下展現良好的元件特性。隨著通道長度逐漸微縮,單閘極電晶體由於其通道控制能力變差,因此特性不易控制的缺點逐一浮現。相較於單閘極電晶體,雙閘極與三閘極電晶體由於通道控制能力有相對維持,因此短通道效應帶來的問題較為緩和。在次32 奈米以下的製程技術,由於完美的閘極控制能力,圓形全閘極電晶體展現許多令人感興趣的結果。
It is known that planar bulk metal-oxide-semiconductor field effect transistors (MOSFETs) play a curcial role in modern microelectronics industry. The device channel nowadays entered sub-100 nanometer (nm) regions; therefore, device material, fabrication technology, and device structure have been of great interests. New device structures may have promising characteristics, and open an interesting research direction.
In this thesis, we study MOSFETs with different gate structures for sub-32 nm technology. Four gate structures, the single-gate, the double-gate, the triple-gate, and the gate-all-around-gate MOSFETs are simulated and compared. We use device simulation software to numerically study the gate structure effect on the electrical characteristics of MOSFETs. The on and off currents, the threshold voltage roll-off, and the short-channel effects are explored and compared. Among device structures, due to perfect channel controbility, results show that the gate-all-around-gate MOSFETs posses fascinating characteristics; in particular, for sub-32 nm technology. We believe that this investigation is useful for MOSFET fabricatin with different gate structures.
誌謝 I
中文摘要 II
中文摘要 II
ABSTRACT III
目錄 IV
圖目錄 V
表目錄 VII
符號目錄 VIII
第一章 緒論 1
1.1 研究動機 1
1.2 研究目的 6
1.3 研究內容 10
1.4 研究方法與流程 12
第二章 不同閘極結構的電晶體 14
2.1 電晶體結構 14
2.2 半導體模式 19
2.3 電腦模擬方法 27
第三章 結果與討論 36
3.1 元件結構設定 36
3.2 基本電位分佈 40
3.3 汲極電流特性 47
3.4 短通道特性 51
第四章 結論與建議 58
4.1 結論 58
4.2 建議 61
參考文獻 63
[1]S. M. Sze, Physics of Semiconductor Devices, Wiley-Interscience, New York 1981.
[2]S. M. Sze, Semiconductor devices, physics and technology, Wiley, New York, 2002.
[3]S. M. Sze, Microelectronics Technology: Challenges in the 21st Century in: S. Luryi, J. Xu, and A. Zaslavsky (Eds), Future Trends in Microelectronics, Wiley-IEEE, 2002, pp. 3-16.
[4]C. Y. Chang and S. M. Sze, ULSI devices, John Wiley & Sons, New York, 2000.
[5]Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, New York, 1998.
[6]T.-S. Chao, Y.-H. Lin, and W.-L. Yang, ” Mobility Enhancement of MOSFETs on p-Silicon (111) With In situ HF-Vapor Pre-Gate Oxide Cleaning”, IEEE Electron Devices Letters, vol. 25, no. 9, pp. 625-627, 2004.
[7]W.-L. Yang, T.-S. Chao and K.-H. Lai, ”Suppression of Boron Penetration in P+-Poly-SiGe Gate P-Channel Metal-Oxide-Semiconductor Field-Effect Transistor Using NH3-Nitrided and N2O-Grown Gate Oxides”, Jpn Journal of Applied Physics, vol. 43, no. 11A, pp. 7462-7463, 2004.
[8]C. Fenouillet-Beranger, T. Skotnicki, S. Monfray, N. Carriere, and F. Boeuf, “Requirements for ultra-thin-film devices and new materials for the CMOS roadmap,” Solid-State Elec. Vol. 48, No. 6, June 2004, pp. 961-967.
[9]B.-Y. Nguyen et al., “Integration challenges of new materials and device architectures for IC applications,” Proc. Int. Integrated Circuit Design and Technology Conf., May 17–20, 2004, pp. 237–243.
[10]S.Watanabe, “Impact of three-dimensional transistor on the pattern area reduction for ULSI,” IEEE Trans. Electron Devices, vol. 50, no. 10, pp. 2073–2080, Oct. 2003.
[11]S. Monfray et al., “50 nm-gate all around (GAA)-silicon on nothing (SON)-devices: A simple way to co-integration of GAA transistors within bulk MOSFET process,” Digest of Technical Papers of The 2002 Symposium on VLSI Technology, Jun. 11–13, 2002, pp. 108–109.
[12]J. P. Colinge, M. H. Gao, A. Romano-Rodriguez, H. Maes, and C. Claeys, “Silicon-on-insulator ‘gate-all-around device’,” Technical Digest of International Electron Devices Meeting (IEDM), Dec. 9–12, 1990, pp. 595–598.
[13]J.-P. Colinge, “Multiple gate SOI MOSFETs,” Solid State Electron., vol. 48, no. 6, pp. 897–905, Jun. 2004.
[14]J. A. Choi, K. Lee, Y. S. Jin, Y. J. Lee, S. Y. Lee, G. U. Leet, S. H. Lee, M. C. Sun, D. C. Kimt, Y. M. Lee, S. G. Bae, J. H. Yang, S. Maeda, N. I. Lee, H. K. Kang, K. P. Suh, “Large Scale Integration and Reliability Consideration of Triple Gate Transistors,” Technical Digest of International Electron Devices Meeting (IEDM), 2004, pp. 647-650.
[15]F.-L. Yang, D.-H. Lee, H.-Y. Chen, C.-Y. Chang, S.-D. Liu, C.-C. Huang, T.-X. Chung, H.-W. Chen, C.-C. Huang, Y.-Chia Y., Y. Li, J.-W. Lee, and P. Chen, M.-S. Liang, and C. Hu, “5nm-Gate Nanowire FinFET,” Digest of Technical Papers of The 2004 Symposium on VLSI Technology, Honolulu, Hawaii, USA, June 15-19, 2004, pp. 196-197.
[16]F.-L. Yang, H.-Y. Chen, F.-C. Chen, C.-C. Huang, C.-Y. Chang, H.-K. Chiu, C.-C. Lee, C.-C. Chen, H.-T. Huang, C.-J. Chen, H.-J. Tao, Y.-C. Yeo, M.-S. Liang, C. Hu, “25 nm CMOS Omega FETs,” Technical Digest of International Electron Devices Meeting (IEDM), 2002, pp. 255-258.
[17]S. Xiong and J. Bokor, “Sensitivity of double-gate and FinFET devices to process variations,” IEEE Trans. Electron Devices, vol. 50, no. 11, pp. 2255–2261, Nov. 2003.
[18]T. Schulz, W. Rosner, E. Landgraf, L. Risch, and U. Langmann, “Planar and vertical double gate concepts”, Solid-State Elec., vol. 46, no. 7, pp. 985-989, July 2002.
[19]H. Wakabayashi, S. Yamagami, N. Ikezawa, A. Ogura, M. Narihiro, K. Arai, Y. Ochiai, K. Takeuchi, T. Yamamoto, and T. Mogami, “Sub-10-nm planar-bulk-CMOS Devices using lateral junction control”, Technical Digest of International Electron Devices Meeting (IEDM), 7-10 Dec. 2003, pp. 20.7.1-20.7.3.
[20]S. Zhang, X. Lin, R. Huang, R. Han, and M. Chan, “A self-aligned, electrically separable double-gate mos transistor technology for dynamic threshold voltage application”, IEEE Transactions on Electron Devices, vol. 50, no. 11, pp. 2297-2300, Nov. 2003.
[21]X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, “Sub 50-nm FinFET: PMOS”, Technical Digest of International Electron Devices Meeting (IEDM), 5-8 Dec. 1999, pp. 67-70.
[22]J. P. Colinge, M. H. Gao, A. Romano-Rodriguez, H. Maes, and C. Claeys, “Silicon-on-insulator gate-all-around device,” Technical Digest of International Electron Devices Meeting (IEDM), 1990, pp. 595-598.
[23]H. Takato, K. Sunouchi, N. Okabe, A. Nitayama, K. Hieda, F. Horiguchi, and F. Masuoka, “Impact of surrounding gate transistor (SGT) for ultra-high-density LSI’s,” IEEE Trans. Elec. Devices, pp. 573-578, 1991.
[24]D. M. Fried, E. J. Nowak, J. KeIdzierski, J. S. Duster, and K. T. Komegay, “A fin-type independent-double-gate NFET”, Proceedings of the 2003 Device Research Conference, June 23-25, 2003, pp. 45-46 .
[25]B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Ho, Q. Xiang, T.-J. King, J. Bokor, C. Hu, M.-R. Lin, and D. Kyser, “FinFET scaling to 10 nm gate length,” Technical Digest of International Electron Devices Meeting (IEDM), Dec. 2002, pp. 251 -254.
[26]M. J. Gilbert and D. K. Ferry, “Efficient quantum three-dimensional modeling of fully depleted ballistic silicon-on-insulator metal–oxide–semiconductor field-effect-transistors,” J. Appl. Phys., vol. 95, no. 12, pp. 7954–7960, Jun. 2004.
[27]S. N. Balaban, E. P. Pokatilov, V. M. Fomin, V. N. Gladilin, J. T. Devreese, W. Magnus, W. Schoenmaker, M. Van Rossum, B. Sorée, “Quantum transport in a cylindrical sub-0.1mm silicon-based MOSFET,” Solid-State Elec., Vol. 46, No. 3, pp. 435-444, March 2002.
[28]N. Sano, A. Hiroki, and K. Matsuzawa, “Device modeling and simulations toward sub-10 nm semiconductor devices”, IEEE Trans. Nanotech., Vol. 1, No. 1, pp. 63-71, Dec. 2002.
[29]T. J. Walls, V. A. Sverdlov, and K. K. Likharev, “MOSFETs below 10 nm: quantum theory”, Physica E, vol. 19, no. 1-2, pp. 23-27, July 2003.
[30]D. K. Ferry, “The onset of quantization in ultra-submicron semiconductor devices,” Superlattices and Microstructures, Vol. 27, No. 2/3, pp. 61-66, Feb. 2000.
[31]R. Venugopal, Z. Ren, S. Datta, M. S. Lundstrom, and D. Jovanovic, “Simulating quantum transport in nanoscale transistors: Real versus mode-space approaches”, J. Applied Physics, Vol. 92, No. 7, pp. 3730-3739, Oct. 2002.
[32]J. R. Watling, A. R. Brown, A. Asenov, A. Svizhenko, and M. P. Anantram, “Simulation of direct source-to-drain tunnelling using the density gradient formalism: Non-Equilibrium Greens Function calibration”, Proc. IEEE Int. Conf. Simulation of Semiconductor Processes and Devices (IEEE SISPAD), 4-6 Sep. 2002 pp. 267 -270.
[33]J. R. Watling, A. R. Brown, and A. Asenov, “Can the Density Gradient Approach Describe the Source-Drain Tunnelling in Decanano Double-Gate MOSFETs?”, J. Comput. Elec., Vol. 1, No. 1-2, pp. 289-293, July 2002.
[34]M. G. Ancona, “Equations of state for silicon inversion layers”, IEEE Trans. Elec. Dev., Vol. 47, No. 7, pp. 1449-1456, July 2000.
[35]M. G. Ancona, Z. Yu, R. W. Dutton, and P. J. Vande Voorde, “Density-gradient analysis of MOS tunneling”, IEEE Trans. Elec. Dev., Vol. 47, No. 12, pp. 2310-2319, Dec. 2000.
[36]A. Schenk and A. Wettstein, “2D Analysis of Source-to-Drain Tunneling in Decananometer MOSFETs with the Density-Gradient Model,” Tech. Proc. Modeling and Simulation of Microsystem, 2002, pp. 552-555.
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