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研究生:郭佑全
研究生(外文):Yu-Chuan Kuo
論文名稱:適用於IEEE802.11a無線區域網路接收端之同步電路設計
論文名稱(外文):VLSI Design of Synchronization Circuit for Receiver of IEEE802.11a WLAN
指導教授:曾憲輝曾憲輝引用關係
指導教授(外文):Hsien-Hui Tseng
學位類別:碩士
校院名稱:逢甲大學
系所名稱:電子工程所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:中文
論文頁數:69
中文關鍵詞:正交分頻多工同步電路
外文關鍵詞:Synchronization CircuitOFDM
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近年來,正交分頻多工 (Orthogonal Frequency Division Multiplexer, OFDM)技術是無線通訊中相當備受矚目的一項技術,由於其具高傳輸率與高頻寬使用率的特性,此技術已被廣泛應用於數位視訊廣播(DAB)、數位音訊廣播(DVB)、數位用戶迴路(xDSL)及無線區域網路標準IEEE 802.11a與HIPERLAN-2。
在OFDM接收機開始解調變載波訊號之前,接收機至少要先完成兩項同步的動作。首先必需先找出封包的邊界,並且立即優化時序來減低ICI與ISI對載波正交性的影響。第二項同步動作便是估計與校正接收信號的頻率誤差,因為任何的誤差均會引入ICI。
本文將依據IEEE802.11a規格書中所訂定的規範來完成時序與頻率同步電路設計。規格書中規定,整個同步系統需以20Mhz的操作頻率來設計。在本文中提出相對應之硬體架構,並以VHDL語言配合Altera之APEX20K600E652-1X驗證版來完成驗證。最後本論文以CIC所建議的流程來完成ASIC設計。
In the recently years, the OFDM(Orthogonal Frequency Division Multiplexer) is a fascinating technique which applied for the wireless LAN (WLAN), the technique have two characteristics that are high transmission rate and high bandwidth usage efficiency, hence, the technique has been applied for Digital Video Broadcast (DVB), Digital Audio Broadcast (DAB), the IEEE802.11a and HIPERLAN-2 standard for wireless LAN (WLAN).
Before an OFDM receiver can demodulate the subcarriers, it has to perform at least two synchronization tasks. First, it has to find out where the symbol boundaries are and what the optimal timing instants are to minimize the effects of inter carrier interference (ICI) and inter symbol interference (ISI). Second it has to estimate and correct for the carrier frequency offset of the received signal, because any offset will be introduced to ICI.
This paper follows the standards of IEEE802.11a to perform the circuit of timing and frequency synchronization. All of the system was designed in frequency at 20MHz. We propose the relative structures of the circuit and use Altera’s APEX20K600E652-1X to implement and verify. Finally, this thesis follows the CIC’s design flow to implement the ASIC.
誌謝...................................................i
摘要..................................................ii
Abstract.............................................iii
目錄..................................................iv
第一章 緒論............................................1
1.1 前言...............................................1
1.2 研究動機...........................................1
1.3 論文大綱...........................................3
第二章 OFDM基本原理....................................4
2.1 OFDM簡介...........................................4
循環置首(Cyclic Prefix)................................8
第三章 IEEE 802.11a 實體層標準........................10
3.1 PLCP Frame Format.................................12
3.2 Overview of the PPDU..............................13
3.2.1 Convolutional Encoder...........................17
3.2.2 Data Interleaving...............................17
3.2.3 Subcarrier Modulation Mapping...................18
第四章 同步演算法.....................................21
4.1 信號偵測..........................................21
4.1.1 時序估測演算法..................................21
4.1.2 IEEE 802.11a信號偵測............................24
4.2 頻率估測..........................................26
4.2.1 頻率偏移之影響..................................26
4.2.2 頻率估測演算法..................................29
4.2.2.1 粗調載波頻率偏移估計..........................29
4.2.2.2 細調載波頻率偏移估計..........................31
第五章 同步電路設計...................................32
5.1 時序估測電路設計..................................32
信號偵測..............................................34
5.2 頻率估測電路設計..................................38
5.2.1 CORDIC (Coordinate Rotation Digital Computer)...39
5.2.2 Sinusoid Iteration Oscillator[11]...............43
第六章 硬體實作與模擬驗證.............................45
6.1 系統規格訂定......................................46
6.2 時序估測電路......................................46
6.2.1 匹配濾波器......................................46
6.2.2信號偵測電路.....................................49
6.2.3邊緣估測(Boundary Estimation)....................51
6.3 頻率估測補償電路..................................52
6.4 CPLD驗證..........................................54
6.5 晶片實現..........................................55
晶片佈局及包裝........................................55
第七章 結論...........................................57
7.1 研究成果..........................................57
7.2 未來發展性........................................57
參考文獻..............................................58
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