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研究生:張朝霖
研究生(外文):Chao-lin Zhang
論文名稱:適用於IEEE802.11a之維特比解碼器電路設計
論文名稱(外文):Design of a Viterbi Decoder for IEEE 802.11a
指導教授:曾憲輝曾憲輝引用關係
學位類別:碩士
校院名稱:逢甲大學
系所名稱:電子工程所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:中文
論文頁數:53
中文關鍵詞:維特比解碼器無線區域網路802.11a
外文關鍵詞:IEEE 802.11aviterbi decoderFPGACPLD
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近年來,數位無線通訊的迅速成長造就了高速資料傳輸的需求,對於頻寬、資料傳輸速度也隨之增加,正交分頻多工(Orthogonal Frequency Division Multiplexing:OFDM)調變技術因此被廣泛應用。OFDM技術主要是可增加抵抗頻率選擇衰減(Frequency Selective Fading)和窄帶干擾(Narrowband Interference)的能力。但在高速度的傳輸下,資料在傳輸過程中保持其正確變得越來越重要,因此錯誤更正碼(Error Correcting Code :EEC)也就扮演著舉足輕重的角色。在接收端中,對於迴旋編碼而言則以維特比解碼演算法(Viterbi Algorithm)具有最大相似解碼,故本論文研究主題為設計符合IEEE 802.11a規格之(2,1,7)維特比解碼器。解碼器架構上結合Compare-Add-Select(CAS)運算與One-Bit Dataflow Structure架構有效運用硬體架構,提升解碼速度。最後,本架構以VHDL撰寫並以CPLD驗證,系統操作頻率可達94.78MHz,所需硬體花費為19,447 Logic Elements,592 Memory bits。
  In recent years, the necessity of the high speed data transmission is induced due to rapid growth of digital wireless communications. For high bit-rate transmission and bandwidth efficiency, OFDM modulation technology had extensive application. OFDM modulation technology can eliminate frequency selective fading and narrowband interference. Under high speed transmission, the correction of data is more and more important. Therefore, FEC plays an important role. At the receiver side, Viterbi algorithm is a maximum likelihood (ML) decoding for Convolutional code. The subject of my research is to design a (2,1,7) Viterbi decoder according with IEEE 802.11a. The architecture combined CAS operation with one-bit dataflow structure to speed up decoding rate. Finally, the new architecture is designed using VHDL and verified in CPLD. 19,447 logic elements were consumed roughly for 94.78MHz system operating clock.
誌謝 ------------------------------------------------------------------------------ I
摘要 ------------------------------------------------------------------------------ II
Abstract ------------------------------------------------------------------------------ III
目錄 ------------------------------------------------------------------------------ IV
圖目錄 ------------------------------------------------------------------------------ VI
表目錄 ------------------------------------------------------------------------------ VIII
第一章 序論 ---------------------------------------------------------------------- 1
1.1 前言 ---------------------------------------------------------------------- 1
1.2 研究動機------------------------------------------------------------------ 2
1.3 研究大綱------------------------------------------------------------------ 3
第二章 IEEE 802.11a 無線區域網路---------------------------------------- 4
2.1 IEEE 802.11a 規格及參數-------------------------------------------- 4
2.2 OFDM 系統------------------------------------------------------------- 7
2.2.1 OFDM 原理--------------------------------------------------- 8
2.2.2 OFDM PLCP--------------------------------------------------- 10
第三章 維特比解碼器概述------------------------------------------------------ 11
3.1 通道模型------------------------------------------------------------------ 12
3.2 最大相似解碼------------------------------------------------------------ 12
3.3 迴旋編碼------------------------------------------------------------------ 14
3.4 維特比解碼器------------------------------------------------------------ 17
3.4.1 維特比解碼架構---------------------------------------------- 17
3.4.2 相加-比較-選擇單元(Add-Compare-Select Unit)------- 18
3.4.3 倖存記憶單元(Survivor Memory Unit)------------------- 21
第四章 研究方法與模擬--------------------------------------------------------- 23
4.1 (2,1,7)迴旋編碼器------------------------------------------------------- 23
4.2 改良式維特比解碼器--------------------------------------------------- 23
4.2.1 CSA(Compare-Select-Add)運算架構---------------------- 24
4.2.2 One-Bit Dataflow Structure架構--------------------------- 26
4.2.3 分支路徑------------------------------------------------------- 27
4.3 分析模擬------------------------------------------------------------------ 27
第五章 硬體實現------------------------------------------------------------------ 36
5.1 系統設計流程------------------------------------------------------------ 36
5.2 改良式維特比解碼器設計與功能模擬------------------------------ 38
5.3 CPLD硬體驗證與測試平台------------------------------------------- 44
5.4 晶片設計------------------------------------------------------------------ 48
第六章 結論---------------------------------------------------------------------- 50
參考文獻------------------------------------------------------------------------------ 52
[1] IEEE std 802.11a, “Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications,” 1999A.

[2] 劉佳炘, “WLAN 802.11a OFDM 的基本架構與功能,”

[3] Qiao Daji, Choi Sunghyun and K.G. Shin,” Goodput Analysis and Link Adaptation for IEEE 802.11a Wireless Lans,” IEEE Transactions, 278 - 292 Oct.-Dec.2002 .

[4] Dusan Matic, “OFDM as a Possible Modulation Technique for Multimedia Applications in the Range Of Mm Waves”.

[5] Prof. L. Vandendorpe, ”Channel Coding and Error Correction in Digital Transmission,” UCL Communications and Remote Sensing Lab.

[6] Shu Lin and Daniel J.Costello, “Error Control Coding,” Upper Saddle River, N.J. c2004.

[7] 李明宗,“腓特比解碼器之路徑計量記憶體連結複雜度之降低研究”, 國立雲林科技大學電子與資訊工程研究所, 2003

[8] G. D. Forney, Jr., “The Viterbi Decoding Algorithm,” IEEE Trans. Inform. Theory, It-15:177-79, January 1969.

[9] M. Boo, F. Arguello and J.D. Bruguera, E.L. Zapata, “ High-Speed Viterbi Decoder: An Efficient Scheduling Method to Exploit the Pipelining,” IEEE International conference, Aug 19-21, 1996.

[10] G. Fettweis and H. Meyr, “High-Speed Parallel Viterbi Decoding: Algorithm and VLSI-Architecture,” IEEE Journal of Communications Magazine, pp.46 – 55, May 1991.

[11] K. Keshab, Parhi, “Novel Pipelining of Msb-First Add-Compare-Select Unit Structure for Viterbi Decoders,” IEEE International Symposium, 23-26, May 2004.

[12] C.B. Shung, P.H. Siegel, G. Ungerboeck and H.K. Thapar, ”VLSI Architectures for Metric Normalization in the Viterbi Algorithm,” IEEE International conference, April 16-19, 1990.

[13] 陳仁和, “適用於正交分頻多工之維特比解碼器晶片設計,” 私立逢甲大學電子工程研究所, 2005.

[14] Engling Yeo, Stephanie Augsburger and Wm. Rhett Davis, “Borivoje Nikolić,
Implementation of High Throughput Soft Output Viterbi,” IEEE Workshop on 16-18 Oct. 2002.

[15] Byonghyo Shim and Jung Chul Suht, “Pipelined VLSI Architecture of the Viterbi Decoder for IMT-2000,” IEEE Telecommunications Conference, pp. 158 – 162, 1999.
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