臺灣博碩士論文加值系統

由於消費型產品仍為電路主要設計的準則，所以低功率設計已經被廣泛研究和使用於各種電路設計之中。近年來雖有許多關於低功率的研究，然而大部份的技術都有一定的複雜度。在本篇論文中，嘗試利用緩昇電壓源(Adiabatic charging)的降低功率消耗原理，找到一個新的低功率設計可以應用於各種電路上，並且完成實際晶片的實作與驗證。我們在這個研究上達成了三個主要目標：首先，我們提供了一個簡單控制電路，實現了緩昇電壓設計技術；第二點，我們以提供並整合元件庫積體電路設計流程(cell-base IC design flow)的技術，方便設計者可以簡單地產生緩昇降電壓之頻率功率管理電路；最後，經過各種電路和實作晶片之後的模擬，證實本論文所設計的電路架構有節省功率消耗的效果。

Because the point of designing circuit still mainly focuses on the consuming products, low power design has been extensively researched and been used on various kinds of circuit. Although there is a lot of research about the low power design in recent years, most of low power design technology is very complex for designer. In the thesis, we try to utilize the principle of adiabatic charging to reduce power consumption, find the new low power design structure that can be applied to various kinds of circuit. And then, we will implement and verify the circuit design. We have reached three main goals in this thesis: First of all, we have offered a simple control circuit to produce adiabatic charging signal in power supply; The second, we combine cell-base IC design flow with the swing-Vdd clock-power management circuit and let the designer easy to produce this swing-Vdd clock-power management circuit; Finally, the simulation result of various kinds of circuit prove that the swing-Vdd clock-power management circuit can reduce a lot of power consumption.

中文摘要 i
ABSTRACT ii
誌謝 iii
目錄 iv
圖目錄 vi
表目錄 viii
第一章 序論 1
1.1 研究動機 1
1.2 論文研究方向與重點 1
1.3 章節安排 2
第二章 相關背景研究 3
2.1 節省dynamic power consumption: Multi_Vdd 4
2.2 節省leakage power consumption: MTCMOS和Gate Power 6
2.2.1 MTCMOS 6
2.2.2 Power gate 7
第三章 緩昇降電壓(CK_VDD)電路 8
3.1 CK_VDD原理基礎 8
3.2 CK_VDD電路架構 11
第四章 設計流程 14
第五章 實驗結果分析 17
5.1 VLD電路運用CK_VDD電路initial_0和initial_1技術 17
5.2 VLD電路加上power management電路架構、initial_0和initial_1技術 19
5.3 VLD電路改進並修正power management電路架構、initial_0和initial_1技術 27
5.4 分析CK_VDD電路架構遇到timing skew問題會有什麼影響 34
5.5 實現5.1節的電路架構應用於VLD設計晶片上 36
5.5.1 佈局驗證結果錯誤說明 38
5.5.2 佈局平面圖 39
5.5.3 打線圖 40
5.5.4 Post-simulation模擬結果 41
第六章 結論 42
參考文獻 43

[1] Habekotte, E.; Stallman, J.; “Several driving configurations with low-voltage input control for a planar power switch”, Solid-State Circuits, IEEE Journal of Volume 19, Issue 1, Feb 1984 Page(s):147 – 154
[2] M. Josephine Ammer, “A Highly Integrated Adiabatic Energy Recovery Digital to Analog Converter” B.S. Computer Science and Engineering Massachusetts Institute of Technology Submitted to the Department of Electrical Engineering and Computer Science in partial fulfillment of the requirements for the degree of Master of Engineering in Electrical Engineering and Computer Science at the MASSACHUSETTS INSTITUTE OF TECHNOLOGY February 1999
[3] M. R.Prasad, D.Kirkpatrick, and R. K.Brayton, “Domino logic synthesis and technology mapping,” presented at the Workshop Notes. Int. Workshop Logic Synthesis, 1997.
[4] T.Thorp, G.Yee, and C.Sechen, “Domino logic synthesis using complex static gates,” in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1998, pp. 242-247.
[5] R. Puri, A. Bjorksten, and T. E. Rosser, “Logic optimization by output phase assignment in dynamic logic synthesis,” in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1996, pp. 2-8.
[6] D.Harris and M. A.Horowitz, “Skew-tolerant domino circuits,” IEEE J. Solid-State Circuits, vol. 32, pp. 1702-1711, Nov. 1997.
[7] R. Puri, “Design issues in mixed static-domino circuit implementations,” in Proc. IEEE Int. Conf. Computer Design, 1998, pp. 270-275.
[8] T.Williams, “Dynamic logic: Clocked and asynchronous,” in Tutorial notes Int. Solid-State Circuits Conf., 1996.
[9] Clock-delayed domino for dynamic circuit design Gin Yee; Sechen, C.; Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Volume 8, Issue 4, Aug. 2000 Page(s):425 - 430