臺灣博碩士論文加值系統

近年來，超寬頻技術的頻率範圍從3.1 – 10.6 GHz已由美國聯邦電信委員會(FCC)所開放出來。本論文主要是針對可應用於IEEE 802.15.3a 標準之3.1 – 10.6 GHz超寬頻無線個人區域網路(WPAN)中。因此本篇論文主要以無線接收機中的超寬頻低雜訊放大器為探討重點。我們知道低雜訊放大器在接收機中主要是扮演接收路徑第一個模組的角色，其中它會影響整體信號頻寬的效能、雜訊指數和整體系統的功率消耗。在寬頻通訊應用中已有多篇文獻皆在探討超寬頻低雜訊放大器的設計，並且有多位研究者提出許多分佈式架構的超寬頻低雜訊放大器。然而，它所要求的是幾個大面積所組成的電感信號延遲線，所以我們必須嘗試去減少晶片面積和功率消耗。
本篇論文所提出的超寬頻低雜訊放大器是由台灣積體電路的RF CMOS 0.18 um製程所實現出來，從設計流程、電路模擬、電路佈局以及晶片量測皆有完整描述。在論文研究中，我們先製作一個全積體化3.1 – 8 GHz超寬頻低雜訊放大器，其中我們採用改良型柴比雪夫帶通濾波電路並且結合電阻式並聯回授電路以達到寬頻輸入阻抗匹配特性。另外在增益級放大器則採用疊接架構去實現放大級電路。在3 .1 – 8 GHz頻率範圍所量測出的輸入反射損耗皆小於-10 dB，最大的功率增益為9.1 dB，-3 dB 頻寬為2 - 9 GHz，1 dB 壓縮點為-4 dBm，偏壓電流在1.8 V電壓供給下為12 mA，總消耗功率為21.6 mW。雖然在模擬結果與量測結果有些許差異，但在找出問題點之後再帶入模擬中仍可維持的相當好的效能。
為了修正以上電路的缺失，我們最後提出了一個電路為全積體化3.1 - 8 GHz超寬頻低雜訊放大器的改良型架構，其操作頻率可從3.1 – 10.6 GHz並且在效能上可達到好的輸入與輸出寬頻匹配、高線性度以及較寬的操作頻寬。另外，在增益平坦度上，操作頻率範圍內皆可維持在1 dB以內。一個全積體化3.1 – 10.6 GHz的超寬頻低雜訊放大器主要是由RC並聯回授電路、改良型柴比雪夫帶通濾波器電路以及中間級電感所組成。量測結果顯示出藉由調整Rf與Cf值，輸入反射損耗(S11)接小於-10 dB。在3 dB頻寬內從2 – 5.8 GHz與6.9 – 10.2 GHz的最大功率增益為8.5 dB與8 dB，操作電壓為1.8 V。偏壓電流為13.8 mA且總功率消耗為24.8 mW。

Recently, the ultra wide-band (UWB) technology has been opened up in the spectrum from 3.1 to 10.6 GHz by the U.S.A Federal Communication Commission (FCC). The purpose of the thesis is aiming at the design and analyses of the ultra wideband low noise amplifier for IEEE 802.15.3a 3.1 – 10.6 GHz band. Therefore, this thesis deals with the UWB radio receiver which is the UWB low noise amplifier (LNA). We know the low noise amplifier (LNA) is the first module in the receiving path of a transceiver, which affects the performance of signal bandwidth, noise figure, and power dissipation of the entire system. Several CMOS LNA design techniques had been reported for broadband communication applications. The well-developed distributed amplifier is known as its wide bandwidth. However, it requires several area consuming inductors to perform signal delay so we must try to reduce the chip size and power consumption.
The proposed UWB LNA was implemented based on TSMC standard 0.18 um RF CMOS process. From the design flow, circuit simulation, layout of circuit, and measurement of chip have been described completely. In a fully integrated 3.1 – 8 GHz UWB LNA structures, we employ Chebyshev band-pass filter circuit and combine shunt-feedback circuit to achieve wideband input impedance matching. In addition, the gain stage amplifier adopts cascode structure to implement amplifier stage. The measured input return loss (S11) is less than -10 dB over 3 – 8 GHz range. The maximum power gain (S21) is 9.1 dB and the -3 dB bandwidth covers 2 – 9 GHz. The 1 dB gain compression performance is approximate -4 dBm. The bias current is 12 mA from a 1.8 V and the power dissipation is 21.6 mW. Although there are some different between measured results and simulation data, after finding the reason and embed in the simulation, the circuit performance still be maintained well.
The last circuit is modified structure of a fully integrated 3.1 – 8 GHz UWB LNA which operating frequency is from 3.1 GHz to 10.6 GHz and the performance can achieve good input/output wideband matching, high linearity, and excellent wide operating bandwidth. Additionally, the gain flatness can be maintained within 1 dB in the whole operating bandwidth. A fully integrated 3.1 – 10.6 GHz UWB LNA consists of RC shunt-feedback circuit, the modified band-pass Chebyshev filter circuit, and the inter-stage gain amplifier. The measured results show that adjusting the values of Rf and Cf, the input return loss (S11) less than -10 dB. The maximum power gain 8.5 dB and 8 dB within the 3 dB bandwidth from 2.1 – 5.8 GHz and 6.9 – 10.1 GHz can be obtained at the operation condition of VDD = 1.8 V. The bias current is 13.8 mA and the power dissipation is 24.8 mW.

Abstract I
Chinese Abstract III
Chinese Acknowledgement V
Contents VI
List of Figures VIII
List of Tables XII

Chapter 1 Introduction 1
1.1 Backgrounds 1
1.2 Motivation 2
1.3 Thesis Organization 3

Chapter 2 The Overview of Ultra Wideband Technology 4
2.1 The History of UWB technology 4
2.2 UWB Standards in IEEE 802.15.3a 6
2.3 Introduction of Multi-Band OFDM 7

Chapter 3 Basic Concepts in LNA Design 11
3.1 Overview 11
3.2 Receiver System Consideration 11
3.2.1 The Concept of Noise Figure 12
3.2.2 Dynamic Range and Minimum Detectable Signal 14
3.2.3 1 dB Compression Point 15
3.2.4 Third-Order Intercept Point and Intermodulation Products 18
3.2.5 Relationships Between 1-dB Compression and IP3 Points 20

Chapter 4 Design and Measurement of A Fully Integrated CMOS 3.1 to 8 GHz Low Noise Amplifier for Ultra Wideband System Application 21
4.1 Overview 21
4.2 Design and Analysis of the UWB LNA 22
4.2.1 Configuration and Transistor Size Selection 22
4.2.2 Bandwidth Extension and Impedance Matching 27
4.3 Simulation and Measurement of the UWB LNA 34
4.3.1 Design flow of Circuit 34
4.3.2 Simulated Results 34
4.3.3 Measured Results 42
4.4 Summary of the UWB LNA Design 47

Chapter 5 Design and Measurement of A Fully Integrated CMOS 3.1 to 10.6 GHz Low Noise Amplifier with Inter-stage Inductor for UWB System Application 49
5.1 Overview 49
5.2 Design and Analysis of the UWB LNA 50
5.3 Simulation and Measurement of the UWB LNA 52
5.3.1 Design flow of Circuit 52
5.3.2 Simulated Results 53
5.3.3 Post-simulation Results 57
5.3.4 Measured Results 63
5.4 Summary of the UWB LNA Design 68
Chapter 6 Conclusions 70
Reference 73

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