臺灣博碩士論文加值系統

隨著極大型積體電路迅速發展，元件尺寸已經進入奈米的領域。同時後段製程之電容、電阻時間延遲及訊號干擾等問題也日益嚴重。為了改善此問題，以極低介電常數材料作為導線間的介電層就成為必要的選擇。本論文提出以電化學置換 (Displacement) 技術，製作各式不同寬度的銅導線。以多孔洞性的材料作為金屬間的介電層，並對介電層做疏水性表面處理，以降低多孔洞性低介電層的k值，使其k值介於1~2之間。此外，本論文也將使用結構較緻密的材質SiC，來作為阻障層，藉由SiC阻障層來改善低介電層與電化學置換銅導線之附著性。
本論文分兩部份進行：
導線方面，利用低成本之電化學置換 (Displacement) 方式，製作各式不同厚度、寬度的銅導線，採用金屬鈦（Ti）、鉭（Ta）作為鑄模材料，分別以TiN和TaN作為阻障層來降低銅膜與底層介電層間的接合應力，並以電性量測觀察其抗電致遷移能力。以旋塗的方式製作多孔洞性結構的低k介電層，以不同氣體對介電層作表面處理，經由電性、物性量測，觀察低k介電層其熱穩定、對銅的阻障能力與漏電流等改善表現。在低k值介電層研究方面，將製作MIS電容結構，以溶凝膠方式備製多孔洞性結構的低k介電層並旋塗的於矽基板上。介電層經疏水性處理後會有矽烷鍵結，但經高溫會有部分斷裂，而產生吸水問題，使得介電常數上升。因此利用不同溫度經由電性、物性量測，觀察低k介電層其熱穩定與漏電流等改善表現。在金屬電極方面，因為多孔低k介電層的組成有TEOS含有矽基源，將利用低成本之電化學置換 (Displacement) 方式，犧牲一層薄的介電層以置換成各式厚度約為150 nm的銅金屬薄膜
再運用第一部份的研究成果，將多孔洞性低k介電層及電化學置換奈米級銅製程整合並進一步的研究與討論；在多孔洞性低k介電層上成長 SiC做為電化學置換銅膜的鑄模材料，再將Si置換成銅膜，再將多孔洞性低k介電層旋塗，最後C以O2熱退火處理氣化後降低導線阻值；其中將探討揮發氣體對低k介電層所造成的影響，最後我們將跟據研究的結果，在不同的奈米銅導線寬度與厚度比例，可得到一個最佳的導線尺寸，奈米銅導線和多孔洞性低k介質材料間的接觸特性及各種製程上所需之材料的最佳選擇，此外，我們也將對置換銅和濺鍍銅、電鍍銅之間作一比較。

As the rapid development of ULSI, the IC device is moving into the sub-micro scale. The performance of integrated circuits will be significantly limited by the interconnect RC delay. To alleviate this impact, using ultra low dielectric constant to replace traditional silicon dioxide as the insulator dielectric layer has become the unavoidable choice. A novel technique to form Cu conductor lines, porous low-k dielectrics films, and SiC will be proposed in this project.
The proposed project will be programmed in two parts schedule.
For the first part, in the conduction wire, using electrochemical displacement method to produce different thickness and widths of Cu interconnect base on Ti and Ta material. Afterwards, we will discussion about electromigration and capacity variation between low dielectric constant. The porous low-k material structure will be used instead of traditional structures. Moreover the hydrophobic treatment will also be adopted to promote the leakage-proof quality of low-k material. Afterwards, we will measure characterization techniques, electrical characterization, thermal stability, leakage current density and barrier ability. The electrochemical displacement method will be utilized to produce different thickness and widths of Cu which are on the porous dielectric films. Then, we will discuss about the electromigration impact on Cu and the capacitance variation for porous dielectric structure, respectively.
For the second part, the porous low-k dielectric approach and Cu displacement method will further be integrated. And therefore, several proposed process techniques will be conducted in the following way. SiC will be deposited upon the porous low-k dielectric as the molding material for Cu films. Then we displace Si with nano Cu by the electrochemical displacement method. The porous low-k dielectric will be span on successively. Finally, the resistance of Copper can de reduced by removing of C atoms by O2 annealing. Every aspect of the proposed process profile above will be explored in great detail, including the trade-off study and the comparisons among those approaches.

Abstract (Chinese)…………………………………………………………………….i
Abstract (English)……………………………………………………………………ii
Acknowledgement (Chinese)………………………………………………………..iv
Contents……………………………………………………………………………...vi
Figure Captions……………………………………………………………………....x
Table Captions………………………………………………………………...........xvi
Chapter 1 Introduction
1.1. Introduction……………………………………………………………………...1
1.1.1. General background….………………………………………………………..1
1.1.2. Difficult challenges…………………………………………………………….2
1.2 Cu Metallization and Low-K dielectrics………………………………………..3
1.2.1 The needs of Cu metallization…………………………………………………3
1.2.2 The needs of low-k dielectrics………………………………………………….4
1.2.2.1 Ultra Low-Κ materials……………………………………………………….6
1.2.2.2 Ultra Low-Κ (Porous Low-Κ)……………………………………………….7
1.3 Cu/Low-K materials and processes……………………………………………..9
1.4 The needs of Cu diffusion barriers………………………………………….....10
1.5 The needs of Cu passivation layers………………………………………….....12
1.6 This organization………………………………………………………………..13
References of Chapter 1…………………………………………………………….23
Chapter 2. A Novel Fabrication of Cu Interconnection by Displacing the Pre-Patterned Ti Film For ULSI
2.1 Fundamental and experimental of electrochemistry background…………...28
2.1.1 Electroless plating of using reducing agent………………………………….28
2.2.2 Seed layers for electroless and electrochemical plating…………………….29
2.3 The theory of the contact displacement……………………………………......30
2.4 Evaluating the thin film………………………………………………………...31
2.5 Experimental…………………………………………………………………….32
2.5.1 Sample preparation…………………………………………………………...32
2.6 Results and Discussion………………………………………………………….33
2.6.1 Selective Cu contact displacement with Ti…………………………………..33
2.6.2 Eletromigration with displacing Cu lines……………………………………35
2.6.3 Line width dependence of electromiration lifetime…………………………36
2.6.4 Line length dependence of electromigration lifetime……………………….37
2.6.5 Line thickness dependence of electomigration lifetime……………………..38
2.7 Conclusion……………………………………………………………………….38
References of Chapter 2…………………………………………………………….54
Chapter 3 Selective Deposition of Cu Interconnects by Pre-Patterned Ta Film
3-1. Electrochemical Cu plating for seed formation and Cu wiring……………..58
3-1-1. Introduction…………………………………………………………………..58
3-2. Experimental…………………………………………………………………...59
3-2-1. Sample preparation………………………………………………………….59
3-4. Results and Discussion…………………………………………………………60
3-4-1. Selective Cu contact displacement with Ta…………………………………60
3-4-2. Microstructure……………………………………………………………….63
3-4-3. Resistivity of Cu lines………………………………………………………..64
3-4-5. Electromigration with displacing Cu lines…………………………………65
3-5. Conclusion……………………………………………………………………...67
Reference of Chapter 3……………………………………………………………..79
Chapter 4 An Ultra-low Dielectric Constant Porous Silica Film with Cu Directly Grown by a Displacement Process
4.1 Introduction……………………………………………………………………..82
4.2 Surface modification on porous silica film…………………………………….83
4-3 Experiment……………………………………………………………………...85
4-3-1 Porous silica film preparation…………………………………………….....85
4-4. Results and Discussion…………………………………………………………87
4-4-1. Selective Cu contact displacement with porous silica……………………..87
4-4-2. Effect of surfactant amount in the coating solutions………………………88
4-4-3. Effect of the amount of acid in the coating solution……………………….89
4-4-4. Effect of the amount of water in the coating solution……………………...91
4-4-5. Bias temperature stress measurements……………………………………..92
4-4-6. Residual stress and stress hysteresis measurements…………………….....93
4-4-7. C-V Characteristics of Cu/Surface Modified Porous/Si Capacitance…….93
4-5. Conclusion……………………………………………………………………...94
Reference of Chapter 4……………………………………………………………108
Chapter 5 Displacing the SiC Barrier directly and the Electrical Characteristics of Bilayer-Structured SiC Dielectric Barriers
5.1 Copper Interconnects Grown by Electrochemical Displacing the Pre-Patterned SiC barrier thin film…………………………………………........111
5.1.1 Introduction………………………………………………………………….111
5.1.2 Experimental…………………………………………………………………112
5.1.2.1 Sample preparation………………………………………………………..112
5.1.3 Results and Discussion………………………………………………………113
5.1.4 Summary……………………………………………………………………..116
5.2 TDDB Reliability Improvement of Cu-Comb Capacitors with Bilayer-Structured SiC Dielectric Barriers………………………………………116
5.2.1 Introduction………………………………………………………………….116
5.2.2 Experimental…………………………………………………………………117
5.2.2.1 Sample preparation………………………………………………………..117
5.2.3 Results and Discussion………………………………………………………118
5.2.4 Summary……………………………………………………………………..122
5.3 Conclusions…………………………………………………………………….122
Reference of Chapter 5……………………………………………………………138
Chapter 6 Conclusions and Further Recommendations
6.1 Conclusions…………………………………………………………………….142
6.2 Further recommendations…………………………………………………….144

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