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研究生:林南聲
研究生(外文):Lin Nan Sheng
論文名稱:控制流程與資料流程結構的快取效能
論文名稱(外文):Cache Performance of Data Flow/Control Flow Architecture
指導教授:周賜福周賜福引用關係
指導教授(外文):Joseph Arul
學位類別:碩士
校院名稱:輔仁大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:英文
論文頁數:62
中文關鍵詞:快取記憶體快取效能可排程資料流程架構
外文關鍵詞:cache memorycache performanceSDF
相關次數:
  • 被引用被引用:0
  • 點閱點閱:252
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  • 下載下載:34
  • 收藏至我的研究室書目清單書目收藏:0
資料流程結構的指令參考動作與一般傳統的系統並不相同。在資料流程的環境之下,程式的執行是靠資料來驅動的,因此資料流程將相依於資料參考的動作。可排程資料流程架構(Scheduled data flow)是一種獨特的結構,其基於資料流程的範例下使用非阻隔式多執行緒(non-blocking multithread)與退耦式(decoupled)的存取模型。資料流程架構的平行運算與依循資料流執行的特性,使其對資料的參考成為二維模式,而這種參考模式與傳統的循序執行模式比較起來更有效率也更加複雜。這個研究比較了資料流程與控制流程的混合結構與現行常見的結構的快取效能。使用非阻隔式多執行緒的模型將程式切割成多個不同的程式區段,而資料的組成與排列提供了一個不可或缺的機制來增進快取的區域性。我們利用幾個測試程式來做評估,這些測試程式在不同數目的快取關連性來展現快取的效能。在大多數的狀況下,可排程資料流程架構的快取效能皆明顯的比傳統系統還好。
Instruction reference in data flow differs from that of conventional systems. In data flow environments, execution is data driven, hence it depends on data reference. Scheduled data flow is a unique architecture that uses a non-blocking multithread and decoupled access model based on data flow paradigm. The parallel nature found in data flow architectures and the dependence of execution on data cause the dimensional reference patterns more effective and complex than the conventional sequential execution. This research compares the cache performance of such hybrid architecture and the existing conventional architecture. By using non-blocking multithreaded model to divide the program into different code sections, data organizations and layouts provide an essential mechanism to improve the cache locality. Our evaluations, with several small benchmarks, demonstrate that the cache performance using different associativity –in most cases, significantly outperform conventional system.
摘要 1
Abstract 2
Table of Contents 3
List of Figures 5
List of Tables 7
Chapter 1. Introduction 9
1.1 Motivation 9
1.2 Organization of This Thesis 11
Chapter 2. Related Works 12
2.1 Cache Memories Performance Improvement 12
2.2 Cache Memories Performance Analysis 13
2.3 Cache memory for Data Flow Architecture 14
Chapter 3. Scheduled Data Flow (SDF) Architecture 17
3.1 Decoupling of Memory Accesses from Execution 19
3.1.1 Execution Pipeline 19
3.1.2 Synchronization Pipeline 20
3.2 Non-blocking Multithreaded Model 22
3.3 Locality of SDF 24
3.3.1 Spatial Locality 25
3.3.1.1 Instructions Reordering 28
3.3.1.2 Example 30
3.3.2 Temporal Locality 32
3.4 Effect of Cache Memory for SDF 34
Chapter 4. Experiment 36
4.1 Experimental Environment 36
4.2 Experimental Results 37
Chapter 5. Analysis of SDF Cache Performance 49
5.1 Instruction Cache 49
5.1.1 Repeated Rate of Code Block 49
5.1.2 Execution Behavior of SDF Programs 51
5.2 Data Cache 51
5.2.1 Frame memory 51
5.2.1.1 Maximum Number of Frame Block 52
5.2.1.2 Size of Frame Block 55
5.2.2 I-Structure memory 57
Chapter 6. Conclusion 59
References 61
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