[1]Nissinen J., Palojarvi P., Kostamovaara J, “A CMOS receiver for a pulsed time-of-flight laser rangefinder,” ESSCIRC Conf., pp. 325-328, Sept. 2003.
[2]Keunoh Park, Jaehong Park, “20 ps resolution time-to-digital converter for digital storage oscilloscopes,” IEEE Nuclear Science Symp., Vol. 2, pp. 876-881, Nov. 1998.
[3]Tian Xia, Hao Zheng, Jing Li, Ginawi A, ”Self-Refereed On-Chip Jitter Measurement Circuit Using Vernier Oscillators,” IEEE Computer Society Annual Symp., pp. 218-223, May 2005.
[4]R. B. Staszewski, D. Leipold, C.-M. Hung, and P. T. Balsara,“TDC-based frequency synthesizer for wireless applications,” in Proc. IEEE Radio Frequency Integrated Circuits (RFIC) Symp., pp. 215-218. June 2004.
[5]Robert Bogdan Staszewski, Sudheer Vemulapalli, “1.3 V 20 ps Time-to-Digital Converter for Frequency Synthesis in 90-nm CMOS,”IEEE Trans. on Circuits and Systems—II, Vol. 53, No. 3, Mar. 2006.
[6]Piotr Dudek, “A High-Resolution CMOS Time-to-Digital Converter Utilizing a Vernier Delay Line,” IEEE Trans. on Solid-State Circuits, Vol. 35, No. 2, Feb. 2000.
[7]Elvi Rgsanen-Ruotsalainen, Timo Rahkonen and Juha Kostamovaara “A Time Digitizer with Interpolation Based on Time-to-Voltage Conversion,” In proc. 40th Midwest Symposium on Circuits and Systems, Vol. 1, pp. 197-200, Aug. 1997.
[8]Elvi Räisänen-Ruotsalainen, Timo Rahkonen, and Juha Kostamovaara “An Integrated Time-to-Digital Converter with 30-ps Single-Shot Precision,” IEEE J.Solid-State Circuits, Vol. 35, No. 10, Oct. 2000.
[9]Poki Chen; Shenz-Iuan Liu; Jingshown Wu, “A Low Power High Accuracy CMOS Time-to-Digital Converter,” IEEE International Symp. Vol. 1, pp. 9-12, June 1997.
[10]Poki Chen, Shen-Iuan Liu, “A cyclic CMOS time-to-digital converter with deep sub-nanosecond resolution,” IEEE Custom integrated Circuits Conf. pp. 605-608, May 1999.
[11]Antonio H. Chan, “A Jitter Characterization System Using a Component-Invariant Vernier Delay Line” IEEE Trans. on VLSI Systems, Vol. 12, No. 1, Jan.2004.
[12]Chorng-Sii Hwang, Student Member, “A High-Precision Time-to-Digital Converter Using a Two-Level Conversion Scheme,” IEEE Trans. on Nuclear Science, Vol. 51, No. 4, Aug. 2004.
[13]Kostas Karadamoglou, Nikolaos P. Paschalidis, “An 11-bit High-Resolution and Adjustable-Range CMOS Time-to-Digital Converter for Space Science Instruments,” IEEE J. Solid-State Circuits, Vol. 39, No. 1, Jan. 2004.
[14]F. Bigongiari, R. Roncella, “A 250-ps Time–Resolution CMOS Multihit Time-to-Digital Converter for Nuclear Physics Experiments,” IEEE Trans. on Nuclear Science, Vol. 46, No. 2, Apr. 1999.
[15]Y. Arai and M. Ikeno,, “A Time Sigitizer CMOS Gate-Array With a 250 ps Time Resolution,” IEEE J. Solid- State Circuits, Vol. 31, pp. 212-220, Feb. 1996
[16]李谷桓,「兩級游標尺延遲線之時間數位轉換器」,碩士論文,國立清華大學,2003。[17]Hee-Tae Ahn and D.J. Allstot, “A low-jitter 1.9-V CMOS PLL for UltraSPARC microprocessor applications,” IEEE J. Solid-State Circuits, Vol. 35, pp. 450-454, Mar. 2000.
[18]W. Rhee, “Design of high-performance CMOS charge pumps in phase-locked loops,” ISCAS Circuits and Systems, Proceedings of the 1999 IEEE International Symposium, Vol. 2, pp. 545-548, 1999.
[19]黃俊仁,「低電壓CMOS全擺幅放大器之設計使用雙重差動輸入對之技巧」,碩士論文,輔仁大學,2004。[20]J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE J. Solid-State Circuits, Vol. 31, pp. 1723-1732, Nov. 1996.