臺灣博碩士論文加值系統

對於需密碼功能服務之嵌入式系統如智慧卡等，差異電力分析 (DPA) 攻擊能藉著側漏的電力資訊快速地破解其密碼。在本篇論文中，我們提出一個多級式預充電遮蓋AND-XOR邏輯(Pre-Charge Masked AND-XOR Logic (PMAXL))來設計密碼硬體模組。透過理論分析及模擬結果顯示，此種邏輯所實現的Advanced Encryption Standard（AES）硬體模組，即便考量短暫雜訊 (glitch)與偏移(skew)等問題，仍可成功地防制差異電力分析之攻擊。此外，只用一般的CMOS 標準元件資料庫就能實現此邏輯型式，乃非常適合使用於半訂製設計。我們在UMC 0.18um製程技術下，成功合成使用PMAXL設計之AES硬體模組。與其他現有的防制方法相較下，PMAXL是個硬體精簡且能確實有效地防制差異電力分析攻擊的防制方法。

Cryptographic embedded systems such as smart cards are vulnerable to Differential Power Analysis (DPA) attacks. In this thesis, we propose a logic design style, called as Pre-Charge Masked AND-XOR Logic (PMAXL), to implement the AES-based cryptographic hardware. Based on theoretical analysis, the PMAXL design makes the device resistant against DPA attacks even considering the glitch and the skew effect. Furthermore, the PMAXL gates can be fully realized using common COMS standard cell libraries. This makes the PMAXL quite suitable for semi-custom design. The PMAXL-based AES hardware module was implemented with UMC 0.18um technology. Compared with existing approaches, the PMAXL design is quite an efficient and feasible countermeasure against DPA attacks.

Abstract (in Chinese) ………………………………………………………………i
Abstract …………………………………………………………………………………ii
Acknowledgement ………………………………………………………………………iii
Contents …………………………………………………………………………………iv
List of Tables …………………………………………………………………………vi
List of Figures ………………………………………………………………………vii
1 Introduction …………………………………………………………………1
1.1 Differential Power Analysis Attack ………………………………1
1.2 Related Works ………………………………………………………………2
1.3 Contributions of This Thesis …………………………………………4
1.4 Organization …………………………………………………………………4
2 The AES Algorithm and Hardware Implementation ………………6
2.1 The Mathematics of GF(28) ……………………………………………6
2.2 The AES Algorithm …………………………………………………………9
2.3 AES Key Expansion ………………………………………………………13
2.4 The AES Hardware Implementation …………………………………14
3 DPA Attacks and Countermeasures …………………………………17
3.1 DPA Attacks …………………………………………………………………17
3.2 Countermeasures …………………………………………………………18
3.3 Glitches and Skew effect ……………………………………………20
4 PMAXL……………………………………………………………………………26
4.1 PMAXL Gates …………………………………………………………………26
4.2 Multi-stage PMAXL ………………………………………………………31
5 Experimental Results ……………………………………………………34
5.1 The DPA-Resistance of PMAXL …………………………………………34
5.2 The AES Hardware Implemented with PMAXL ………………………36
5.3 Experimental Results ……………………………………………………37
6 Conclusions …………………………………………………………………39
References ………………………………………………………………………………40
Appendix A ………………………………………………………………………………43

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