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研究生:張育瑋
研究生(外文):Yo-Wei Chang
論文名稱:5.8GHzCMOS射頻前端接收電路晶片設計
論文名稱(外文):5.8GHz CMOS Front-End Circuit Design
指導教授:姚嘉瑜
指導教授(外文):Chia-Yu Yao
學位類別:碩士
校院名稱:華梵大學
系所名稱:電子工程學系碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:中文
論文頁數:74
中文關鍵詞: 射頻 802.11a WLAN 低雜訊放大器 平衡器 主動式電感 混波器 放大器
外文關鍵詞:RF802.11aWLANLow noise amplifierPassive balunActive inductorGilbert cell mixerSingle-Ended amplifier.
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本論文以UMC 0.18um CMOS製程來應用於802.11a WLAN 5.8GHz CMOS射頻前端接收電路,晶片上包括了低雜訊放大器(Low noise Amplifier) 、被動式平衡器(Passive Balun) 、主動式電感(Active Inductor) 、混波器(Mixer) 、放大器(Amplifier) 。

在電路的設計上,RF Port為5.725~5.825GHz,經LO Port為5.237~5.337GHz降頻至IF Port為488MHz。低雜訊放大器增益為18.26dB,雜訊指數為2.38dB,Input P1dB為-26.5dBm,Output P1dB為-9.69dBm;混波器轉換增益為33.62dB,雜訊指數為15.38dB,Input P1dB為-31.9dBm,Output P1dB為-0.61dBm;整體射頻前端接收電路在1.8V的工作電壓下可得到43.56dB的增益,雜訊指數為6.88dB,Input P1dB為-41.1dBm,Output P1dB為1.05dBm。
This thesis presents a 802.11a WLAN 5.8GHz CMOS Front-End circuit design in UMC 0.18um CMOS process. The chip contains Low Noise Amplifier, Passive Balun, Active Inductor, Gilbert Cell Mixer and Single-Ended Amplifier.

The RF spectrum specification is from 5.725~5.825GHz, the LO is from 5.237GHz~5.337GHz, and the IF is at 488MHz. The low noise amplifier exhibits a gain of 18.26dB, noise figure of 2.38dB, input P1dB at -26.5dBm, and output P1dB at -9.69dBm. The Gilbert cell mixer exhibits a conversion gain of 33.62dB, noise figure of 15.38dB, input P1dB at -31.9dBm and output P1dB at -0.61dBm. The whole CMOS Front-End circuit exhibits a gain of 43.56dB, noise figure of 6.88dB, input P1dB at -41.1dBm and output P1dB at 1.05dBm.
誌謝.......................Ⅰ
中文摘要.....................Ⅱ
ABSTRACT....................Ⅲ
目錄.......................Ⅳ
表錄.......................Ⅵ
圖錄.......................Ⅶ
一、緒論....................1
1.1 簡介....................1
1.2 研究動機..................3
二、射頻接收電路原理及設計...........5
2.1 RF電路簡介.................6
2.2 RF設計參數考量...............8
2.2.1 雜訊...................8
2.2.2 線性度及失真...............16
三、5.8GHz射頻前端接收電路設計.........26
3.1 5.8GHz射頻前端接收電路架構.........26
3.2 低雜訊放大器................26
3.2.1 簡介..................27
3.2.2 低雜訊放大器原理及架構.........29
3.2.3 低雜訊放大器模擬結果..........36
3.3 被動式平衡器...............42
3.3.1 被動式平衡器設計原理及架構.......42
3.3.2 被動式平衡器模擬結果..........42
3.4 主動式電感................43
3.4.1 主動式電感設計原理及架構........43
3.4.2 主動式電感模擬結果...........45
3.5 混波器..................47
3.5.1 簡介..................47
3.5.2 混波器的原理及架構...........47
3.5.3 Gilbert cell Mixer模擬結果........56
3.6 5.8GHz射頻前端接收電路模擬結果........64
四、結論......................71
參考文獻......................72
參考文獻

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