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研究生:涂君豪
研究生(外文):Jiun-Hau Tu
論文名稱:具五類單元之心臟收縮式陣列平方器
論文名稱(外文):A Systolic Array Squarer Having Five Classes of Cells
指導教授:蔣元隆蔣元隆引用關係
指導教授(外文):Yuan-Long Jeang
學位類別:碩士
校院名稱:國立高雄應用科技大學
系所名稱:電子與資訊工程研究所碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:中文
論文頁數:80
中文關鍵詞:平方器心臟收縮式陣列管線式
外文關鍵詞:SquarerSystolic Arraypipeline
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平方器電路已經被廣泛地運用在各種方面,例如:數位訊號處理(DSP),微處理器中的算術邏輯單元(ALU),以及影像壓縮….等方面,為一種相當普遍且使用率頻繁的電路架構。平方器電路可以利於解決影像龐大且複雜的資料量,而目前常見的平方器電路架構為平行處理(Parallel)平方器演算法、布斯(Booth)平方器演算法、Redundant平方器演算法等等,以上這三種演算法所實現的平方器電路,其共同特點為所運用的邏輯閘數目少,功率較省,但缺點就是反應速率非常慢,如用在處理大量影像以及複雜訊號上,整體系統的效能將會因此而大打折扣的。
在本篇論文中,我們提出一種具五類單元之心臟收縮式陣列平方器,其包含一個心臟收縮陣列,該心臟收縮陣列依據每一級運算所需相關之管線化及規則性結構進行分類,以形成五類單元模組,再將該五類單元模組依架構圖組合完成平方器。該五類單元模組分別由數個全加器、半加器及數個AND邏輯閘選擇組成。藉此,該五類單元模組適用於處理大量數位訊號資料,且具有提升處理速率、降低硬體成本及減少功率消耗。
The squarer circuit has been used in many applications, such as digital signal processing (DSP), arithmetic logic unit (ALU) in the microprocessor, in the image compression etc. Squarer circuit can be used in solving the huge and complicated image data processing. Current famous squarer circuit structures are parallel processing squarer algorithm, Booth squarer algorithm, Redundant squarer algorithm...etc., these three algorithms are similar in few for the logic gates and low power to made use of. However, the weakness is that the processing velocity is very slow, as when used in handling a huge amount and sophisticate of image signals.
In this paper, we propose a systolic array squarer having five classes of cells by pipelining and regulation of each operational circuit. Each of the cell modules is selected from a group consisting of plural full adders, plural half adders and plural AND gates. Therefore, the systolic array with the five cell modules are suitable for applying to process a great number of digital signals, with speeding up processing time, and lower hardware cost and power consumption.
目 錄

中文摘要 ------------------------------------------------- i
英文摘要 ------------------------------------------------- ii
誌謝 ------------------------------------------------- iii
目錄 ------------------------------------------------- iv
表目錄 ------------------------------------------------- vi
圖目錄 ------------------------------------------------- vii
第一章 前言--------------------------------------------- 1
1.1 研究背景--------------------------------- 1
1.2 研究資料回顧------------------------------ 1
1.3 研究動機與研究方法--------------------------------------- 2
1.4 各章提要---------------------------------------- 3
第二章 心臟收縮式陣列的介紹---------------------------------- 5
2.1 簡介----------------------------------------------- 5
2.2 心臟收縮式陣列的定義--------------------------------- 5
2.3 心臟收縮式陣列的特性---------------------------------- 7
2.4 心臟收縮式陣列資料的交流方式--------------------------- 8
2.5 心臟收縮式陣列的結構------------------------------------- 8
2.6 心臟收縮(Systolic)的實用演算法 -------------------------- 12
2.7 心臟收縮式陣列的應用 ----------------------------------- 13
2.8 本章結論與平方器演算法的應用與探討 ----------------------- 14
第三章 各種乘法器和平方器演算法的相關介紹 ----------------------- 16
3.1 簡介 -------------------------------------------------- 16
3.2 Parallel演算法的乘法器和平方器原理 ------------------------ 16
3.2.1 Parallel演算法的乘法器原理 ------------------------------ 16
3.2.2 Parallel演算法的平方器原理 ------------------------------- 18
3.3 Booth演算法的乘法器和平方器原理 -------------------------- 20
3.3.1 Booth演算法的乘法器原理 ---------------------------------- 20
3.3.2 Booth演算法的平方器原理 ---------------------------------- 24
3.4 Redundant演算法的乘法器和平方器原理 ------------------- 27
3.4.1 Redundant演算法的乘法器原理 ------------------------------ 27
3.4.2 Redundant演算法的平方器原理 ------------------------------ 30
第四章 心臟收縮式陣列平方器之設計方法與電路模擬結果 -------- 33
4.1 簡介--------------------------------------------------- 33
4.2 平方器設計之結構演化過程---------------------------------- 33
4.3 設計流程圖--------------------------------------------- 40
4.4 電路架構簡化過程與動作原理說明----------------------------- 41
4.5 電路模擬結果討論----------------------------------------- 52
4.6 電路規格表與先前技術之比較-------------------------------- 64
第五章 結果討論與未來展望---------------------------------------- 66
參考文獻 ------------------------------------------------------- 67
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[11]Yoo, J.-T.; Smith, K.F.; Gopalakrishnan, G.; “A fast parallel squarer based on divide-and-conquer” Solid-State Circuits, IEEE Journal of , Volume: 32 , Issue: 6 , June 1997 Pages:909 – 912
[12]Strollo, A.G.M.; De Caro, D.; “Booth folding encoding for high performance squarer circuits” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on] , Volume: 50 , Issue: 5 , May 2003 Pages:250 – 254
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