臺灣博碩士論文加值系統

在多樣性的電子產品應用中，攜帶型個人化電子產品，如手機、MP3隨身聽等等的使用量急劇增加，而目前在各種電子產品的IC晶片上的供應電壓是以低電壓、高速度為趨勢。例如Flash晶片上的供應電壓是3.3V，但是IC電路上有些電路無法適用如此低電壓驅動，例如在SPI(Serial Peripheral Interface)元件中或是標準元件(Standard Device)中通常需要較高的電壓去驅動記憶體陣列(Memory Array)或是快閃記憶體陣列(Flash Memory Array)，而在快閃記憶體(Flash Memory)中，NOR的控制閘需要12V而NAND的控制閘需要20V的電壓供應，以利用熱電子注入(Hot Electron Injection)或是F-N穿隧(Fowler Nordheim Tunneling)完成寫入或是讀取的動作。
本論文利用P-MOS二極體(P-MOS Diode)加上電容，設計出兩組非揮發性升壓電路，使得在互補式金氧製程下的電晶體每一個端點的電壓都可以避免接面崩潰或是閘極到通道崩潰的情形發生，此外也設計出兩組穩壓電路及兩組內建震盪器以完成SoC(System on Chip)。輸入電壓為3.3V，經由數個層級耦合及穩壓後，我們可個別得到DC12V與DC20V的電壓輸出。此外，此設計也以TSMC 0.18um CMOS製程設計套件加上ESD(Electro Static Discharges)防護輸出電路，完成晶片模擬。完成之晶片尺寸為705×978um2。

In a variety of electric product applications, the electric products of carryon or personal style, the utility quantity of mobile phone and MP3 player have rapidly increased, and the trend of supply voltage is low voltage as well as high speed on IC chip for many electric products. While the supply voltage is 3.3V on flash products, some circuits can not drive in IC with this low voltage. The instance of SPI device or standard device normally needs high voltage to drive memory array or flash memory array. In flash memory, the supply voltage of control gate of NOR device must require12V and that of NAND device must achieve 20V. Those will complete the writing actions or reading actions by hot electron injection or F-N tunneling mechanism.
This thesis proposes the structure of P-MOS diodes plus some capacitors, to provide two non-volatile booster circuits. Every connecting point in circuits will avoid the occurrence of dielectric breakdown in gate oxide or p-n junction. Besides, we also design two stable voltage circuits and two internal oscillators for SoC(system on chip). As the input voltage is 3.3V, to couple the voltage and to stabilize the voltage after several stages, we can separately obtain the output voltage with DC12V and DC20V, respectively. Furthermore, this circuit design also adopts the process design kits of TSMC 0.18um triple-well process with protective output circuits of ESD to approach the chip protection. The final dimension of this chip size is around 705×978um2.

中文摘要--------------------------------------------------- i
英文摘要---------------------------------------------------ii
誌謝------------------------------------------------------iii
目錄-------------------------------------------------------iv
表目錄-----------------------------------------------------vi
圖目錄----------------------------------------------------vii
第一章 緒論------------------------------------------------1
第二章 快閃記憶體操作簡介----------------------------------3
2.1 寫入與擦式機制-----------------------------------3
2.1.1 通道電子注入與寫入---------------------------3
2.1.2 F-N穿遂寫入----------------------------------5
2.1.3 快閃記憶體F-N穿遂擦拭------------------------6
2.1.4 快閃記憶體操作-------------------------------7
2.1.5 NOR和NAND快閃記憶體的差別--------------------9
第三章 倍壓電路原理---------------------------------------11
3.1 狄克森充電幫浦介紹------------------------------11
3.1.1 金氧半導體基本操作原理----------------------12
3.1.2 金氧半導體-二極體基本操作原理---------------13
3.1.3 狄克森充電幫浦之架構------------------------17
3.1.4 狄克森充電幫浦之操作原理--------------------18
3.2 狄克森充電幫浦之電性分析------------------------20
第四章 非揮發性升壓電路的設計、模擬與佈局-----------------27
4.1 非揮發性升壓電路之介紹---------------------------27
4.1.1 非揮發性升壓電路之設計架構------------------27
4.1.2 升壓電路之操作說明--------------------------29
4.1.3 升壓電路在設計上的優點與缺失----------------32
4.2 DC12V、DC20V升壓電路之設計-----------------------34
4.2.1 DC20V與DC12V升壓電路模擬與佈局--------------34
4.3 穩壓電路與震盪電路之設計-------------------------41
4.3.1 穩壓電路的模擬與佈局------------------------42
4.3.2 震盪器之模擬與佈局--------------------------45
4.4 升壓電路整體模擬與比較---------------------------46
4.4.1 升壓電路整體模擬與佈局----------------------46
4.4.2 升壓電路之比較------------------------------48
第五章 非揮發性升壓電路的最佳化---------------------------53
5.1 震盪信號測試-------------------------------------53
5.1.1 環形震盪器測試------------------------------53
5.2 非揮發性升壓電路整體模擬-------------------------60
5.2.1 DC20V升壓電路整體模擬-----------------------60
5.2.2 DC12V升壓電路整體模擬-----------------------63
5.3 製程考量-----------------------------------------65
5.3.1 升壓電路在單井製程結構上的狀況--------------65
5.3.2 升壓電路在三井製程結構上的狀況--------------68
5.4 非揮發性升壓電路之完整佈局與特性-----------------72
5.4.1 DC20V的升壓電路佈局修正---------------------72
5.4.2 非揮發性升壓電路的特性----------------------75
5.4.3 非揮發性升壓電路在溫度變化下之特性----------76
5.4.4 非揮發性升壓電路在輸入電壓變化下之狀況------77
第六章 結論與未來展望-------------------------------------78
參考文獻---------------------------------------------------79
附錄
A 佈局之DRC與LVS結果----------------------------------81

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