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[1]G. Huinan, D. Lee and G.P. Li, An Analytical Model for Optimization of Programming Efficiency and Uniformity of Split Gate Source-Side Injection SuperFlash Memory, IEEE Trans. Electron Devices, Vol. 50, pp. 809-815, 2003. [2]D. Mark, M. Kennard, Y. Melaku, N. Benjamin, T. J. King and C. Hu, Gate Oxide Thickness and Gate Poly-Si Etching Condition Dependence, IEEE International Symposium, pp. 56-59. 1998. [3]H.S. Shin, J.W. Kim, Y.S. Seol and I.H. Choi, Sub-Quarter-Micron Al Etching Technology Using SiON Hard Mask in Transformer Coupled Plasma Etcher, IEEE Microprocesses and Nanotechnology, pp. 218-219, 1999. [4]K. Miwa and Y. Kawabata, In-situ Quantification of Deposition Amount in a Poly-Si Etch Chamber using Optical Emission Spectroscopy of Etching Plasma, IEEE Semiconductor Manufacturing, Vol. 30, pp. 95-98, 2003. [5]N. Masatoshi and T. Ken, Advanced Gate Etching for Accurate CD Control for 130-nm Node ASIC Manufacturing, IEEE Semiconductor Manufacturing, Vol. 17, pp. 281-285, 2004. [6]W.H. Lee, D.K. Lee, Y.H. Na, K.S. Kim, K.O. Ahn, K.D. Suh, and Y. Roh, Impact of Floating Gate Dry Etching on Erase Characteristics in NOR Flash Memory, IEEE Trans. Electron Devices, Vol. 23, pp. 476-478, 2002. [7]S. Alba, O.Vassalli, G. Valentini, and P. Colombo, Effect of Plasma, Pressure and RF Bias on Electron Shading Damage, IEEE International Symposium,Vol. 22-24, pp. 50-53, 2000. [8]Y.M. Huang, C.H. Lin, and C.N. Hsiao, Method of Forming Poly Tip of Floating Gate in Split-Gate Memory, United States Patent, No. 6653188B1, 2003. [9]張鼎張,半導體製程技術導論,Chapter 7, pp. 224-228, 2001. [10]B. Yeh and Y.W. Hu, Method of Self-Aligning a Floating Gate to a Control Gate and to an Isolation in an Electrically Erasable and Programmable Memory Cell, United States Patent, NO. 6429075B2, 2001.
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