此論文主要研究一種單一變壓耦式(TCP)蝕刻方法以形成具一對矽尖角之微渠道製程，此具矽尖角之微渠道可當做快閃記憶體中之浮置閘極，以提高其資料抹除之效率。研究過程中首先製作含有一矽層之基底，然後將該基底置於一蝕刻機台之反應室中，利用蝕刻氣體並施以一射頻功率回蝕上述之矽層，以使被蝕刻矽層之中間低於兩側，以構成一對矽尖角。研究中分別討論蝕刻氣體之成分、反應室壓力與射頻功率對矽尖角之角度與基底矽層底部凹缝形成之影響，所考慮之蝕刻氣體由不等比例之氯氣(Cl2)、氧氣(O2)、氦氣(He)、溴化氫(HBr)所組成；蝕刻機台之上射頻功率固定為600 W，下射頻功率分別考慮為10 W與20 W；而反應室壓力則分別為4、5、6 與10 mTorr；研究之結果發現，在下射頻功率為20 W，而反應室壓力設定為10 mTorr的條件下，當調整蝕刻氣體中之氯氣為20.4%、氧氣為5.5%、氦氣為12.9%與溴化氫為61.2%時，以進行乾式蝕刻，即可形成一底部無凹縫之矽尖角。

A single transformer coupled plasma dry etching (TCP) process for forming a micro-channel with a pair of silicon tips was investigated. This micro-channel can act as a floating gate in a flash memory to increase erase speed. In each experiment, a substrate with a silicon layer was carefully prepared. This substrate was placed in the reaction chamber of a TCP etching machine. By passing an etching gas mixture through the substrate and processing it with a radio frequency power, a concavity was formed on the silicon layer. The middle region at the bottom of the concavity would be lower than the edge region, a silicon tip was thus obtained. In this work, the effects of etching gas composition, chamber pressure and radio frequency power on the angle of silicon tip and bottom dimple were investigated. The considered etching gas mixture comprises of Cl2, O2, HBr, and He. The upper radio frequency power was fixed at 600 W and the lower radio frequency power was either at 10 W or at 20 W. Three chamber pressures, 4.5, 6, and 10 mTorr, were individually considered. The result shows that for the case with the lower radio frequency power of 20 W, chamber pressure of 10 mTorr and the Cl2, O2, HBr, and He composition setting at 20.4%, 5.5%, 12.9%, 61.2%, a silicon tip without bottom dimple can be formed.

中文摘要…………………………………………………………….…....... i
英文摘要………………………………………………………….……....... ii
目錄……………………………………………………………….…….….. iii
表目錄……………………………………………………………….....…... vi
圖目錄………………………………………………………………..…...... vii
符號說明……………………………………………………………....….... ix

第一章 緒論................................................................................................ 1
1.1 前言....................................................................................... 1
1.2 文獻回顧............................................................................... 2
1.3 研究內容與目的................................................................... 6

第二章 實驗設備與過程........................................................................... 7
2.1 實驗之設備.......................................................................... 7
2.1.1 實驗材料................................................................. 7
2.1.2 TCP乾蝕刻系統..................................................... 7
2.1.3 掃描式電子顯微鏡................................................. 8
2.1.4 化學氣相沉積......................................................... 8
2.1.5 步進對準機及塗佈顯影機..................................... 9
2.1.6 光阻去除機…......................................................... 9

2.2 乾蝕刻之理論模式.............................................................. 9
2.2.1 電漿之形成............................................................. 10
2.2.2 離子轟擊................................................................. 11
2.2.3 化學蝕刻…............................................................. 11
2.2.4 物理蝕刻................................................................. 11
2.2.5 本研究之蝕刻模式................................................. 12

2.3 實施方式.............................................................................. 14

2.4 各組實驗之條件.................................................................. 15
2.4.1 溴化氫含量變化之實驗......................................... 15
2.4.2 反應室壓力變化之實驗......................................... 16
2.4.3 射頻功率變化之實驗............................................. 16
2.4.4 氯氣與氧氣含量變化之實驗................................. 16
2.4.5 氣 體 壓 力固 定為6 mTorr下 溴 化 氫 含量變化 之實驗.……………………...…………………………. 17
2.4.6 氣體壓力固定為10 mTorr下溴化氫含量變化之實驗…………………………..................................... 17

第三章 實驗結果....................................................................................... 18
3.1 溴化氫含量的影響.............................................................. 18
3.2 反應室壓力的影響.............................................................. 18
3.3 射頻功率的影響…………………….................................. 19
3.4 氯氣與氧氣的影響………………….................................. 19
3.5 氣體壓力固定為6 mTorr下溴化氫含量之影響............... 19
3.5.1 溴化氫為30 sccm時之結果.................................. 19
3.5.2 溴化氫為60 sccm時之結果.................................. 20
3.5.3 溴化氫為90 sccm時之結果.................................. 20
3.6 氣體壓力固定為10 mTorr下溴化氫含量之影響............. 21
3.6.1 溴化氫為30 sccm時之結果…….......................... 21
3.6.2 溴化氫為60 sccm時之結果…….......................... 21
3.6.3 溴化氫為90 sccm時之結果…….......................... 21

第四章 結論............................................................................................... 23
4.1 結論...................................................................................... 23
4.2 未來展望.............................................................................. 25

參考文獻....................................................................................................... 26

[1]G. Huinan, D. Lee and G.P. Li, An Analytical Model for Optimization of Programming Efficiency and Uniformity of Split Gate Source-Side Injection SuperFlash Memory, IEEE Trans. Electron Devices, Vol. 50, pp. 809-815, 2003.
[2]D. Mark, M. Kennard, Y. Melaku, N. Benjamin, T. J. King and C. Hu, Gate Oxide Thickness and Gate Poly-Si Etching Condition Dependence, IEEE International Symposium, pp. 56-59. 1998.
[3]H.S. Shin, J.W. Kim, Y.S. Seol and I.H. Choi, Sub-Quarter-Micron Al Etching Technology Using SiON Hard Mask in Transformer Coupled Plasma Etcher, IEEE Microprocesses and Nanotechnology, pp. 218-219, 1999.
[4]K. Miwa and Y. Kawabata, In-situ Quantification of Deposition Amount in a Poly-Si Etch Chamber using Optical Emission Spectroscopy of Etching Plasma, IEEE Semiconductor Manufacturing, Vol. 30, pp. 95-98, 2003.
[5]N. Masatoshi and T. Ken, Advanced Gate Etching for Accurate CD Control for 130-nm Node ASIC Manufacturing, IEEE Semiconductor Manufacturing, Vol. 17, pp. 281-285, 2004.
[6]W.H. Lee, D.K. Lee, Y.H. Na, K.S. Kim, K.O. Ahn, K.D. Suh, and Y. Roh, Impact of Floating Gate Dry Etching on Erase Characteristics in NOR Flash Memory, IEEE Trans. Electron Devices, Vol. 23, pp. 476-478, 2002.
[7]S. Alba, O.Vassalli, G. Valentini, and P. Colombo, Effect of Plasma, Pressure and RF Bias on Electron Shading Damage, IEEE International Symposium,Vol. 22-24, pp. 50-53, 2000.
[8]Y.M. Huang, C.H. Lin, and C.N. Hsiao, Method of Forming Poly Tip of Floating Gate in Split-Gate Memory, United States Patent, No. 6653188B1, 2003.
[9]張鼎張，半導體製程技術導論，Chapter 7, pp. 224-228, 2001.
[10]B. Yeh and Y.W. Hu, Method of Self-Aligning a Floating Gate to a Control Gate and to an Isolation in an Electrically Erasable and Programmable Memory Cell, United States Patent, NO. 6429075B2, 2001.