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研究生:黃致喨
研究生(外文):Chih_Liang Huang
論文名稱:適用於電池操作裝置之低電壓零靜態電流脈波頻率調變升壓式轉換器
論文名稱(外文):Low Voltage, Zero Quiescent Current PFM Boost Converter for Battery-operated Devices
指導教授:張振豪
指導教授(外文):Robert C. Cheng
學位類別:碩士
校院名稱:國立中興大學
系所名稱:電機工程學系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:英文
論文頁數:69
中文關鍵詞:零靜態電流脈波頻率調變升壓式轉換器
外文關鍵詞:zero quiescent currentpulse frequency modulationboost converter
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摘要

本論文內容主要是設計一個脈波頻率調變升壓式的轉換器,其具有低工作電壓與零靜態電流消耗的特點。現今,體積小、重量輕、長待機時間正是電池操作之可攜式電子裝置的發展趨勢;針對於這些趨勢與發展,論文中提出一個低電壓與零靜態電流的電路技術,其不但可以降低工作電壓為一顆鎳氫電池的電壓(1.2伏特或1.5伏特),更可藉由零靜態電流的消耗之故,有效地延長可攜式電子裝置的待機時間。

此外,能隙參考電壓電路為轉換器中不可或缺的組成電路之ㄧ,其輸出參考電壓對溫度變化的抵抗能力,會直接影響轉換器輸出電壓的精確性;所以,一個具有新溫度補償機制的能隙參考電壓電路,亦在論文中被提出,其主要是利用一溫度補償產生器電路,針對不同的溫度區間加以補償,以提高輸出參考電壓對溫度變化的抵抗能力,進而提升轉換器輸出電壓的精確性。

本論文中的轉換器電路,是使用台灣積體電路製造股份有限公司所提供之0.35µm 2P4M 3.3V/5V 混合訊號互補金氧半導體製程來加以實現,整體晶片的面積為1.5×1.5mm²。
ABSTRACT

A PFM boost converter which has the advantages of the low supply voltage and zero quiescent current consumption is proposed in this thesis. Nowadays, the trends of the battery-operated portable electronic devices are small volume, light weight and long stand-by time. Due to these trends, a low voltage and zero quiescent current technique for the converter is needed. It not only can reduce the supply voltage to a single cell battery voltage, for example 1.2Volts or 1.5Volts, but also can extend the service time (stand-by time) of the portable electronic devices by the zero quiescent current consumption.

Besides, a bandgap reference circuit is an essential component of the converter. Because the output reference voltage is affected by the temperature variation, the precision of the output voltage of the converter will also be affected directly. Hence, a new bandgap reference circuit with a temperature compensation mechanism is proposed in this thesis. It mainly utilizes a temperature compensation generator to compensate the temperature variation of the output reference voltage in different temperature zones. Therefore, a higher precision output voltage of the converter which will be affected less by temperature variation can be obtained.

In this thesis, the converter is implemented by using the TSMC 0.35µm 2P4M 3.3V/5V CMOS process and the total chip area is 1.5×1.5mm².
CONTENTS


ACKNOLODGEMENTS .............................................. i
摘要 ......................................................... ii
ABSTRACT ...................................................... iii
CONTENTS ...................................................... iv
LIST OF FIGURES ............................................... vi
LIST OF TABLES ................................................ ix

Chapter 1 Introduction
1.1 Background and Overview ................................ 1
1.2 Motivation ............................................. 8
1.3 Thesis Organization .................................... 9
Chapter 2 Existing and Proposed PFM Boost Converter
2.1 Fundamentals of the Conventional PFM Boost Converter ... 10
2.1.1 The Existing PFM Boost Converter with Fixed Frequency
Control .................................................... 15
2.1.2 The Existing PFM Boost Converter with Current Limited
Control .................................................... 16
2.2 Proposed Improvements .................................. 17
2.2.1 Low Voltage and Zero Quiescent Current Technique ..... 18
2.2.2 Temperature Compensation Technique ................... 20
Chapter 3 System and Sub-circuits Design
3.1 System Architecture .................................... 21
3.2 Bias Circuit ........................................... 23
3.3 Voltage Detector ....................................... 25
3.4 Temperature Compensated Bandgap Reference Circuit ...... 27
3.5 Hysteresis Comparator .................................. 39
3.6 Off-time Generator ..................................... 42
3.7 Current Limiter ........................................ 44
3.8 Ring Oscillator ........................................ 50
3.9 Driving Circuit ........................................ 52
3.10 Control Logic Circuits ................................ 53
Chapter 4 Simulation Results and System Implementation
4.1 Simulation Results ..................................... 57
4.2 Layout View ............................................ 62
4.3 Performance Summary .................................... 64
Chapter 5 Conclusions and Future Work
5.1 Conclusions ............................................ 66
5.2 Future Work ............................................ 67
References ................................................. 68


LIST OF FIGURES


Figure 1.1 Battery-operated and portable electronic device ........ 1
Figure 1.2 Applications of the Power Management ICs ............... 2
Figure 1.3 Simplified diagram of the low dropout regulator (LDO) .. 3
Figure 1.4 Simplified diagram of the switching regulator (buck type) 3
Figure 1.5 Simplified structure of the buck converter ............. 4
Figure 1.6 Simplified structure of boost converter ................ 5
Figure 1.7 Simplified structure of buck- boost converter .......... 5
Figure 1.8 Pulse-Width Modulation mode ............................ 6
Figure 1.9 Pulse-Frequency Modulation mode ........................ 7
Figure 1.10 Continuous-conduction mode ............................ 7
Figure 1.11 Discontinuous-conduction mode ......................... 8
Figure 2.1 Simplified diagram of the conventional PFM boost converter 9
Figure 2.2 Relation of the inductor current and ON/OFF time ........ 12
Figure 2.3 Completed structure of the existing PFM boost converter
with fixed frequency control ....................................... 15
Figure 2.4 Completed structure of the existing PFM boost converter
with current limited control ....................................... 16
Figure 2.5 Supply voltage of the existing boost converter .......... 18
Figure 2.6 Supply voltage of the new boost converter ............... 19
Figure 2.7 Design concept of the new bandgap reference circuit ..... 20
Figure 3.1 Completed architecture of the low voltage
and zero quiescent current PFM boost converter .................... 21
Figure 3.2 Timing diagram of the boost converter at VGATE node ..... 22
Figure 3.3 Schematic of the bias circuit ........................... 23
Figure 3.4 Bias current (IBIAS) versus the supply voltage .......... 24
Figure 3.5 Startup circuit transient test .......................... 25
Figure 3.6 Schematic of the voltage detector ....................... 25
Figure 3.7 Waveforms of the voltage detector ....................... 26
Figure 3.8 Corner simulation of the voltage detector ............... 27
Figure 3.9 Schematic of the conventional bandgap reference circuit . 27
Figure 3.10 Diagram of the temperature compensation generator ...... 29
Figure 3.11 Schematic of the proposed bandgap reference circuit .... 30
Figure 3.12 Three compensated temperature zones .................... 31
Figure 3.13 Frequency response of the operational amplifier ........ 32
Figure 3.14 Output reference voltage versus temperature
(the conventional bandgap reference circuit) ..................... 33
Figure 3.15 Output reference voltage versus temperature
(the proposed bandgap reference circuit) ........................... 33
Figure 3.16 Power supply rejection ratio of the conventional B.G.R . 34
Figure 3.17 Power supply rejection ratio of the proposed B.G.R...... 34
Figure 3.18 Current consumption of the temperature compensation generator
@3.6V supply........................................................ 35
Figure 3.19 Startup circuit of the proposed B.G.R. @3.6V supply
and 140?C .......................................................... 35
Figure 3.20 Supply variation (a) 1.8V, (b) 2.7V, (c) 3.6V versus
output reference voltage (VREF =0.405V~0.395V) ..................... 36
Figure 3.21 Corner simulation of the proposed B.G.R. @1.8V supp..... 36
Figure 3.22 Corner simulation of the proposed B.G.R. @2.7V supply .. 37
Figure 3.23 Corner simulation of the proposed B.G.R. @3.6V supply .. 37
Figure 3.24 Schematic of the hysteresis comparator ................. 39
Figure 3.25 Propagation delay time of the comparator ............... 40
Figure 3.26 Hysteresis voltage of the comparator ................... 40
Figure 3.27 Offset voltage of the comparator ....................... 41
Figure 3.28 Schematic of the off-time generator .................... 42
Figure 3.29 Waveforms of the off-time generator .................... 43
Figure 3.30 Schematic of the current limiter ....................... 44
Figure 3.31 Frequency response of the operational amplifier ........ 46
Figure 3.32 Offset voltage of the operational amplifier ............ 46
Figure 3.33 Input common mode range of the operational amplifier ... 47
Figure 3.34 Output swing of the operational amplifier .............. 47
Figure 3.35 Waveforms of the current limiter ....................... 49
Figure 3.36 Schematic of the ring oscillator ....................... 50
Figure 3.37 Feedback system of the oscillator ...................... 50
Figure 3.38 Waveforms of the ring oscillator ....................... 51
Figure 3.39 Schematic of the driving circuit ....................... 52
Figure 3.40 Propagation delay time of the driving circuit .......... 53
Figure 3.41 Schematic of the (a) inverter (b) two input NAND gate
(c) three input NAND gate .......................................... 54
Figure 3.42 Schematic of the (d) AND gate (e) OR gate .............. 55
Figure 3.43 Schematic of the multiplex ............................. 55
Figure 3.44 Schematic of the S-R latch ............................. 55
Figure 3.45 Schematic of the divider ............................... 56
Figure 4.1 Probe nodes of the simulation ........................... 57
Figure 4.2 Test condition I ........................................ 58
Figure 4.3 Test condition II ....................................... 59
Figure 4.4 Test condition III ...................................... 60
Figure 4.5 Power Efficiency @ VOUT=1.8V ............................ 61
Figure 4.6 Power Efficiency @ VOUT=3.6V ............................ 61
Figure 4.7 Layout of (a) the proposed converter and (b) bandgap
reference circuit .................................................. 62


LIST OF TABLES


Table 3.1 Comparisons of the conventional and proposed B.G..R. ...... 38
Table 3.2 Performances of the hysteresis comparator ................. 41
Table 3.3 Aspect ratio of the operational amplifier ................. 45
Table 3.4 Performances of operational amplifier ..................... 45
Table 4.1 Comparisons of the existing and
the proposed bandgap reference circuits ............................. 64
Table 4.2 Comparisons of the existing and
the proposed boost converters ....................................... 65
References


[1]‘‘Product Information,’’http://www.benq.com.tw/.
[2]‘‘Solution Card,’’ http://www.analog.com.tw/english/index.asp
[3]Maxim, ‘‘Regulator Topologies for Battery-powered Systems,’’ Application Note 660, Jan 31, 2001.
[4]Marty Brown, ‘‘Power Supply Cookbook, ’’ 2nd ed., Butterworth-Heinemann, 2001.
[5]Shih-Chieh Liao, ‘‘Low Current Pulse-Frequency Modulation Converter, ’’ M.S. thesis, Feng-Chia University, June, 2004.
[6]Hsueh-kun Lu, ‘‘Research and Development for White LED Drive Integrated Circuit, ’’ M.S. thesis, Fu-Jen University, July, 2004.
[7]P.E. Allen, D.R. Holberg, ‘‘CMOS Analog Circuit Design, ’’ 2nd ed., Oxford, 2002.
[8]J. Sheng, Z. Chen and B. Shi, “A 1V supply area effective CMOS bandgap reference,” Proceedings of the 5th International Conference on ASIC, vol. 1, pp. 619-622, Oct. 2003.
[9]G. A. Rincon-Mora and P. E. Allen, “A 1.1-V current-mode and piecewise-linear curvature-corrected bandgap reference,” IEEE J. Solid-State Circuits, vol. 33, pp. 1551-1554, Oct. 1998.
[10]Chi Yat Leung, Philip K. T. Mok and Ka Nang Leung, “A 1-V integrated current-mode boost converter in standard 3.3/5-V CMOS technologies,” IEEE J. Solid-State Circuits, vol. 40, no. 11, pp. 2265-2274, Nov. 2005.
[11]B. Razavi, “Design of Analog CMOS Integrated Circuit,” McGraw Hill, 2002.
[12]Hung-Yu Lin, “Implementation and Application of Pulse Width Modulation Circuit and Inductance Current Sensing Circuit,” M.S. thesis, Lung-Hwa University of Science and Technology, June, 2004.
[13]Chi Yat Leung, Ka Nang Leung and P.K.T. Mok, “Design of a 1.5-V high-order curvature-compensated CMOS bandgap reference,” IEEE International Symposium on Circuits and Systems, vol. 1, pp, 48-52, May 2004.
[14]K. N. Leung, P.K.T. Mok and C. Y. Leung, “A 2-V 23-μA 5.3-ppm/oC curvature-compensated CMOS bandgap voltage reference,” IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 561-564, March 2003.
[15]P.L. Miribel-Catala, M.Puig-Vidal, J.S. Marti, P. Goyhenetche, X. Q. Nguyen, “An integrated digital PFM DC-DC boost converter for a power management application-- a RGB backlight LED system driver, ” IEEE Industrial Electronics Society, vol. 1, pp.37-42, Nov. 2002.
[16]“AIC1642: 3-Pin One-Cell Step-Up DC/DC Converter,’’ Aanlog Integrations Corporation Inc.
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