由於網際網路的應用與服務的迅速發展，目前一般以軟體為基礎架構的網路設備可能不足以負擔未來網路服務的要求，例如:在V4與V6混合的網路協定環境中，路由器必須要能處理IPv4/IPv6之間的轉換，並且同時要能維持網路協定(Internet Potocol)的處理速度與傳輸線路一樣。
本論文提出一個整合式的系統晶片(System On Chip)架構完成快速路徑的封包發送與處理，並且將需要特殊處理的封包留給處理器處理，例如:封包路線表的更新與網路廣播的發送協議。在此一系統中，主要利用Xilinx嵌入式SOC發展系統軟體與Xilinx的現場可編程邏輯陣列閘(Field Programmable Gate Array, FPGA)Vertex_II_P30作為發展平台。
本系統的硬體架構包含IBM的嵌入式處理器 (Power PC)、CoreConnect系統匯流排 (On Chip Peripheral Bus 與 Processor LocalBus) 、乙太網路控制模組 (Ethernet Medium Access Control) 、外部記憶體控制模組、與封包引擎（Packet Engine）模組。封包引擎模組是我們自行設計的封包處理模組，主要用來代替處理器處理一般常規性的快速路徑的封包，目的在於減少處理器的工作量與封包處理的時間。
實驗結果方面， 我們將展示簡化的IPv4和IPv6封包的處理結果，並且比較軟體處理與硬體處理的性能。最後由結果得知，我們所設計的封包引擎具有較快的處理速度。

Due to the diversity of internet applications and services, traditional software-based networking devices may not be sufficient to afford the processing load imposed by the services. One example is the mixed-version IP environment in which routers must handle the IPv4/IPv6 translation while keeping the IP processing at the line speed.
Previous packet process design may be use processor or ASIC approach, they usually has problems of performance or flexibility. This thesis is to present a System on Chip (SOC) solution for handling the fast-path packet forwarding, and leave the control data, such as packets from routing or specific protocols, being processed by a CPU.
The proposed packet engine, which handles the fast-path data, is designed as pipeline structure in order to maximize the throughput. The solution utilizes the IBM Power PC processor core, CoreConnect Bus peripheral, Xilinx Embedded Development Kit, and Xilinx Vertex_II_Pro Field Programmable Gate Array (FPGA).
In the experimental results, we will show results of packet processing of IPv4 and IPv6, and compare the performance by showing the throughput and the processing delay. The better performance can be obtained in the hardware-implemented engine than those generated by the software-based engine with the same length packet.

Chinese abstract i
English abstract iii
Acknowledgment iv
Contents v
List of Tables vii
List of Figures viii
List of acronyms and abbreviations x
1 Introduction 1
1.1 Motivation 1
1.2 Translation mechanism 2
1.3 Reduced IPv6 Feature 3
1.4 Limitations 3
1.4.1 Software 3
1.4.2 Hardware 4
2 Technology and Background 5
2.1 System on Chip (SoC) solutions 5
2.1.1 System on Chip or Microcontroller 5
2.2 Application Specific Integrated Circuit (ASIC) 6
2.3 Programmable logic device (PLD) 6
2.3.1 Field Programmable Gate Array (FPGA) 6
2.3.2 Simple Programmable Logic Device (SPLD) 7
2.3.3 Complex Programmable Logic Device (CPLD) 7
2.4 Hardware Description Language (HDL) 8
3 System Overview 9
3.1 Power PC, PLB, OPB, and PLB - OPB Bridge 11
3.1.1 Power PC 11
3.1.2 PLB, OPB, and PLB-OPB Bridge 12
3.2 The OPB Ethernet Media Access Controller (EMAC) 14
4 The System bus Architecture 17
4.1 The Bus Architecture 17
4.2 Bus Master Protocol 18
4.3 Intellectual Property Interface (IPIF) 19
5 The Packet Engine Module Architecture 22
5.1 The Packet Engine 22
5.2 Identification Code Word 24
5.3 Ingress Module 26
5.4 Egress Module 27
5.5 Control core 29
5.6 Classification and Route Module 31
5.7 V6 Packet header process module 34
5.8 V4 Packet Header Process module 36
5.9 Power PC Interrupt Module 37
5.10 Interrupt module 38
5.11 Buffer Block 40
5.12 Memory content 41
6 Experimental Results 44
6.1 The results of the IPv4 Packet Processing 45
6.2 The results of the IPv6 Packet Processing 49
6.3 The performance of the OPB bus Transaction 53
6.4 The performance of Packet Engine Transaction 54
7. The Conclusions and Future Work 58
Reference 60
Appendix A 62
Appendix B 64

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