臺灣博碩士論文加值系統

電流驅動式數位類比轉換器具有能直接驅動外面負載的特性，故被廣泛使用於高速的應用上，但其效能往往受靜態與動態線性度的限制。在本篇論文，一種稱為隨機式資料加權平均技術的動態元件匹配類的隨機取樣被運用在轉換器中，來降低因為製程不匹配所造成的諧波失真。不僅如此，結合所提出的新式佈局技巧能更有效的提升上述的技術。此外，當數位類比轉換器操作在高頻時，輸出的突波便會影響轉換器的效能，而歸零機制也因此成為消除輸出突波的最佳選擇。但傳統的歸零機制多半將輸出強制接地，突如其來的電壓變化將使電流隨之改變而產生額外的失真。因此，本篇提出能保持切換負載一致的新型歸零機制。新型的歸零機制能確保機制在切換時尚能保持環境一致，即時在高速操作時，也能保持較高的無雜訊動態範圍。
使用上述新提出之技術，本篇論文實現出一個低功率、小面積的十四元位、每秒一百百萬次操作頻率的電流驅動式數位類比轉換器。此數位類比轉換器包含使用隨機式資料加權平均技術的五位元最大位元與高位的最小位元，而此十元位使用熱碼編碼，低位最小位元則維持使用二元碼。轉換器的輸出放置一新式的歸零機制，以使轉換器在高頻輸出時，還能保持較高的效能。此轉換器所含的面積僅0.26 mm2，採用TSMC 0.18微米、1P6M CMOS 製程。經由模擬得知，此轉換器在低頻輸出能達到89dB的無雜訊動態範圍，即使輸出到達Nyquist-rate，也有69dB的無雜訊動態範圍。在1.8伏的電源供應下，類比電路之功率消耗為21mW，數位電路之功率消耗為3mW。

Current-steering digital-to-analog converters (DACs) can drive the external loading directly in high-speed applications. However, the performance of these current-steering DACs is determined by both the static and dynamic linearity. In this thesis, a DEM-like algorithm called “Random Multiple Data-Weighted Averaging, RMDWA” is accomplished to diminish the harmonic distortions resulted from process mismatches with its simple circuit design. BM rotated walk layout technique is proposed to increase the effect. Besides, the DACs also suffer from the glitches when they are operated at high speed. The return-to-zero (RTZ) switching scheme becomes a best candidate to eliminate the glitches from transients. Nevertheless, conventional RTZ schemes are the ways which are shorted the output to the ground. Abrupt voltage change results in current variations and more distortions. A proposed return-to-zero scheme with constant switching load can keep the same environments when transients and can maintain the high spurious free dynamic range (SFDR) in high-speed operations.
Using the antecedent of new techniques, a low-power and small-area 14-bit 100-MHz current-steering DAC is implemented in this thesis. The DAC includes a 5-bit MSBs and ULSBs with thermometer decoders and RMDWA algorithm and 4-bit binary-coded LLSBs. A new return-to-zero switching scheme is placed in output of DAC to maintain the high-performance at high-speed output frequency. It just occupies 0.26mm2 in a TSMC 0.18um 1P6M CMOS process. In the simulation, the SFDR achieves 89dB at the lower output frequency, and 69dB at the Nyquist-rate output frequency with operated frequency of 100MS/s. The power consumptions are 21mW for analog circuits and 2mW for digital circuits from a 1.8V supply.

1 Introduction.............................................1
1.1 Motivation...............................................1
1.2 Organization.............................................2

2 Nyquist-Rate Digital-to-Analog Converter.................3
2.1 Digital-to-Analog Converter Fundamentals.................3
2.1.1 Ideal DAC................................................4
2.1.2 Static Performance.......................................5
2.1.3 Dynamic Performance......................................8
2.1.4 Spectrum Specification...................................9
2.2 Binary-Weighted DAC Architecture.........................13
2.2.1 Resistor-String DAC......................................14
2.2.2 R-2R Ladder DAC..........................................15
2.2.3 Charge Redistribution DAC................................15
2.2.4 Current-Steering DAC.....................................17
2.3 Thermometer-Coded DAC Architecture.......................18
2.4 Segmented DAC Architecture...............................19
2.5 Summary..................................................20

3 System Analysis and Design of DAC........................21
3.1 Mismatch of Current Source...............................21
3.1.1 Gradient Error Distributions.............................21
3.1.2 Random Error.............................................24
3.1.3 Minimum Required Matching and Size of Current Sources....25
3.2 Finite Output Impedance of Current Source................28
3.3 Number of Thermometer Code...............................31
3.4 Random Multiple Data-Weighted Averaging Algorithm........32
3.4.1 Traditional Data-Weighted Averaging Algorithm............32
3.4.2 Random Multiple DWA Algorithm............................34
3.5 Layout Techniques........................................38
3.5.1 QN Rotated Walk Layout Scheme............................38
3.5.2 Proposed BM Rotated Walk Layout Scheme...................41
3.6 Return-to-Zero Scheme....................................45
3.6.1 Conventional-Voltage Shorted RTZ.........................45
3.6.2 Proposed RTZ of Constant Switching Load..................47
3.6.3 Applications for RTZ.....................................51
3.7 Summary..................................................52

4 Circuit Design of DAC....................................53
4.1 DAC Architecture.........................................53
4.2 Current Cell.............................................54
4.2.1 Cascode Current Source...................................54
4.2.2 Bias of Current Cell.....................................56
4.3 High-Speed Latch.........................................58
4.4 Digital Circuit..........................................61
4.4.1 Linear Feedback Shift Register Circuit...................61
4.4.2 Binary-to-Thermometer Decoder............................63
4.4.3 RMDWA Control Circuit....................................64
4.5 Layout...................................................67
4.6 Summary..................................................70

5 Simulation Result and Measurement........................71
5.1 Simulation Results.......................................71
5.2 Measurement Setup........................................77

6 Conclusion and Future Work...............................78

Reference........................................................79

[1]B. Razavi, "Principles of Data Conversion System Desing," NJ: IEEE Press, 1995.
[2]Milael Gustavsson and J. Jacob Wikner, "CMOS Data Converters for Communications," Boston, 2000.
[3]Yonghua Cong and Randall L. Geiger, "Switching Sequence Optimization for Gradient Error Compensation in Thermometer-Decoded DAC Arrarys," IEEE Transactions on Circuit and System II, VOL. 47, pp. 585-595, July 2000.
[4]G. Van der Plas, J. Vandenbussche, W. Sansen, M. Steyaert, and G. Gielen, "A 14-bit intrinsic accuracy Q2 random walk CMOS DAC," IEEE Journal of Solid-State Circuits, VOL. 34, pp. 1708-1718, Dec. 1999.
[5]Yonghua Cong and Randall L. Geiger, "A 1.5-V 14-Bit 100-MS/s Self-Calibrated DAC," IEEE Journal of Solid-State Circuits, VOL. 38, NO. 12, pp. 2051-060, Dec. 2003.
[6]Alex R. Bugeja, "High-speed, high-precision digital-analog converters designed for spectral performance," PhD dissertation, University of Illinois at Urbana-Champaign, 2000.
[7]Qiuting Huang, Pier Andrea Francese, Chiara Martelli, and Jannik Nielsen, "A 200MS/s 14b 97mW DAC in 0.18um CMOS," IEEE Solid-State Circuits Conference, Dig. Tech. Papers, pp. 364-365, 2004.
[8]K. D. Chen and T. H. Kuo, " An Improved Technique for Reducing Baseband Tones in Sigma-Delta Modulators Employing Data Weighted Averaging Algorithm without Adding Dither," IEEE Transactions Circuits and System II, VOL. 42, pp. 753-762, Dec. 1995.
[9]T. H. Kuo, K. D. Chen, and H. R. Yeng, "A wideband CMOS Sigma-Delta Modulator with Incremental Data Weighted Averaging," IEEE Journal of Solid-State Circuits, VOL. 37, pp. 11-17, May. 1996.
[10]Yu-Hong Lin, "A 16-bit, High-Speed DAC with Random Multiple Data-Weighted Averaging Algorithm," Master dissertation, National Cheng Kung University, Taiwan, 2002.
[11]Yu-Hong Lin, Da-Huei Lee, Chen-Chung Yang, and Tai-Haur Kuo, "High-Speed DACs with Random Multiple Data-Weighted Averaging Algorithm," International Symposium on IEEE Circuits and System, VOL. 1, pp. I-993 - I-996, May 2003.
[12]Kuan-Dar Chen, "Automatic Coefficients Synthesis and Circuit Implementation Techniques of High-Order Sigma-Delta Modulators," PhD dissertation, National Cheng Kung University, Taiwan, 2000.
[13]J. Bastos, A. Marques, M. Steyaert, and W. Sansen, "A 12-bit intrinsic accuracy high-speed CMOS DAC," IEEE Journal of Solid-State Circuits, VOL. 33, pp. 1959-1969, Dec. 1998.
[14]B. Razavi, "Design of Analog CMOS Integrated Circuits," McGraw-Hill, 2001.
[15]M. J. M. Pelgrom et. al., "Matching Properties of MOS Transistors." IEEE Journal of Solid-State Circuits, VOL. 24, pp. 1433-1439, Dec. 1989.
[16]I. Galton and P. Carbone, "A Rigorous Error Analysis of D/A Conversion with Dynamic Element Matching," IEEE Transactions on Circuit and System II, VOL. 42, Dec. 1995.
[17]L. R. Carley, "A Noise-shaping Coder Topology for 15+ bit Converters," IEEE Journal of Solid-State Circuits, VOL. 24, pp. 267-273, Apr. 1989.
[18]T. Miki, Y. Nakamura, M. Nakaya, S. Asai, Y. Akasaka, and Y. Horiba, " An 80-MHz 8-bit CMOS D/A Converter," IEEE Journal of Solid-State Circuits, VOL. SC-21, pp. 983-988, Dec. 1986.
[19]Alex R. Bugeja, Bang-Sup Song, "A self-trimming 14-b 100-MS/s CMOS DAC," in IEEE Journal of Solid-State Circuits, VOL. 35, NO. 12, Dec. 2000.
[20]Qiuting Huang, Pier Andrea Francese, Chiara Martelli, Jannik Nielsen, "A 200MS/s 14b 97mW DAC in 0.18μm CMOS," in IEEE Solid-State Circuits Conference, VOL 1, pp.364-532, Feb. 2004.
[21]Alex R. Bugeja, Bang-Sup Song, Patrick L. Rakers, Steven F. Gillig, "A 14-b, 100-MS/s CMOS DAC designed for spectral performance," IEEE Journal of Solid-State Circuits, VOL. 34, NO. 12, Dec. 1999.
[22]Martin Clara, Wolfgang Klatzer, Andreas Wiesbauer, Dietmar Straeussnigg, "A 350MHz low-OSR ΔΣ Current-Steering DAC with Active Termination in 0.13μm CMOS," IEEE Solid-State Circuits Conference, VOL.1, pp.118-588, Feb. 2005
[23]Anne Van den Bosch, Marc A. F. Borremans, Michel S. J. Steyaert and Willy Sansen, "A 10-bit 1-Gsample/s Nyquist Current-Steeering CMOS D/A Converter," IEEE Journal of Solid-State Circuits, VOL. 36, NO. 3, pp. 315-324, Mar. 2001.
[24]Mika P. Tiilikainen, "A 14-bit 1,8-V 20-mW 1-mm2 CMOS DAC," IEEE Journal of Solid-State Circuits, VOL. 36, NO. 7, pp. 1144-1147, July 2001.