臺灣博碩士論文加值系統

　　本論文主要針對UWB 射頻收發機CMOS晶片進行研究與製作。論文中首先介紹UWB系統架構，接著針對寬頻射頻積體電路建議使用分散式主動電路，分散式主動電路可製作多種的射頻前端電路。吾人也嘗試以分散式主動電路製作應用於UWB系統的射頻前端電路晶片製作，包括分散式放大器、分散式低雜訊放大器、分散式射頻開關和整合射頻開關與放大器及低雜訊放大器成為單一射頻前端晶片，晶片製作均使用國家晶片中心(CIC)所提供的TSMC 0.18μm製程，晶片量測採用打鎊線至PCB測試板或用晶片探針進行量測。
　　3-10 GHz分散式射頻開關量測結果可發現此電路之插入損耗確實達成寬頻之要求，於10GHz時插入損耗為4.4dB 。3-10GHz分散式放大器量測結果為，S11<-5dB、S22<-9dB、S12<-22dB、S21=5.4~11dB、IIP3=0.5~5.1dBm@3~6GHz、input P1dB為-8.8~-0.4dBm，output P1dB為3.1~7.6dBm，OIP3為13.4~16.7dBm @3~6GHz，受限於儀器IIP3和OIP3只量測到6GHz以下，消耗功率為34.2mW，PAE@6GHz ICP為14.6％。3-10 GHz分散式低雜訊放大器模擬結果為，S11<-10dB、S22<-10dB、S12<-47dB、S2>19dB、雜訊指數5.1~5.8dB、IIP3為-13.3dBm、IP1dB為-21~-17dBm，消耗功率為16mW。
　　在3-10 GHz CMOS UWB射頻前端晶片方面，transmitter模擬結果為，增益11~13.7dB，雜訊指數5.1dB~5.8dB，輸入返回損耗大於10dB，輸出返回損耗大於10dB，output P1dB=1dBm@6.5GHz，OIP3=8dBm@6.5GHz，group delay=100±50ps。receiver模擬結果為，增益13.5~15.2dB，雜訊指數4.2dB~6.2dB，輸入返回損耗大於10dB，輸出返回損耗大於10dB，input P1dB=-18.5dBm@6.5GHz，IIP3=-8.5dBm@6.5GHz。

　UWB radio frequency transceiver based on TSMC CMOS technology is mainly researched and fabricated. Introducing UWB systematic structure at first, then distributed active circuits for the wide-band radio frequency integrated circuit is proposed in this paper. The distributed active circuits can be implemented in many kinds of radio frequency front-end circuit. RF front-end integrated chip including distributed amplifier, low nose amplifier and switch is presented and they are also fabricated respectively. TSMC 0.18μm process offered by National Chip Implementation Center (CIC ) is adopted . These chips are measured on PCB board or on-wafer.
　In 3-10 GHz distributed RF switch, the measurement result of Insertion loss can be satisfied for wide-band communication system, it is insertion loss as 4.4dB at 10GHz. It demonstrated that the ultra wide-band RF switch may be achieve in standard CMOS process, but the insertion loss and the noise figure are too high for UWB radio system. The noise figure (NF) usually require less than 7 dB for UWB systematic receiver. The RF switch is the key circuit in the front of the low noise amplifier, the insertion loss of switch is equal to the noise figure of received signal for LNA. Therefore, how to improve the insertion loss is very important, the methods of improving are 1.Channel width of NMOS must be dwindling for use. 2. The loss of pad effect must be omitted. 3. Parasitic capacity of trace of layout must be small.
　In 3-10 GHz distributed amplifier, the results of measurement are S11<-5dB, S22<-9dB, S12<-22dB, S21 is 5.4~11dB, IIP3 is 0.5~5.1dBm@3-6GH, Input P1dB is -8.8~-0.4dBm, Output P1dB is 3.1~7.6dBm, OIP3 is 13.4-16.7dBm@3-6GHz, power consumption is 34.2mW, and PAE@ICP is 14.6% at 6GHz, respectively. In 3-10 GHz distributed low noise amplifier, the result of simulation are S11<-10dB , S22<- 10dB , S12<- 47dB , S12> 19dB , NF =5.1-5.8dB , IIP3 is -13.3dBm , P1dB is -21~-17dBm, and power consumption is 16mW, respectively.
　In 3-10 GHz COMS UWB radio frequency front circuit, transmitter (amp. + T/R switch) simulation result, it is gained as 11-13.7dB, the noise figure is 5.1-5.8dB, input return loss is greater than 10dB, output return loss is greater than 10dB, output P1dB is 1dBm@6.5GHz, OIP3 is 8dBm@6.5GHz, and Group Delay is 100±50ps, respectively. Receiver (T/R switch + LNA) simulation result, it is gained as 13.5-15.2dB, the NF is 4.2-6.2dB, input return loss is greater than 10dB, output return loss is greater than 10dB, input P1dB is -18.5dBm@6.5GHz, and IIP3 is -8.5dBm@6.5GHz, respectively.

目 錄
第一章 緒論 Introduction 1
1.1 UWB的研究背景 1
1.2 UWB的定義 2
1.3 UWB的特性 3
1.4 UWB的系統架構 5
1.5 DS-CDMA與MB-OFDM 技術比較 6
1.6 DS-CDMA與MB-OFDM鏈路預算(Link budget) 9
1.7 無線個人網路及無線區域網路通訊協定 12
1.8 論文架構 14
第二章 分散式主動電路的概論 15
2.1 分散式電路系統[7] 15
2.1.1 無限長傳輸線 16
2.1.2 有限長傳輸線 17
2.1.3 射頻積體電路中的有限長傳輸線[11] 20
2.2 計算分散式放大器之增益[8][9] 23
2.2.1 影像參數法 23
2.2.2 CMOS 場效電晶體的高頻等效電路模型之 與 27
2.2.3 傳統行波分散式放大器CTWDA的增益[14] 28
2.2.4 串接單級分散式放大器CSSDA的增益[9] 33
2.2.5 CTWDA與CSSDA的比較[9] 35
2.2.6 檢視以CMOS製程製作的分散式放大器之現況回顧 36
2.3 傳統分散式放大器的應用[9][10] 37
2.3.1 分散式射頻開關 37
2.3.2 分散式混波器 38
2.3.3 分散式壓控振盪器DVCO 40
2.3.4 分散式倍頻器 41
2.3.5 分散式阻抗轉換器 41
2.3.6 分散式功率結合器和分歧器和循環器及平衡器 43
第三章 CMOS分散式射頻開關 44
3.1 T/R切換開關使用開關元件 44
3.1.1 PIN Diode 切換開關 45
3.1.2 GaAs MESFET 切換開關 45
3.1.3 CMOS切換開關 46
3.2 典型CMOS T/R切換開關的電路設計 48
3.3 3~10GHz分散式CMOS T/R切換開關的電路設計 52
3.3.1 電路設計 52
3.3.2 模擬與量測結果 60
3.3.3 結果與討論 65
第四章 3~10GHz分散式串接單級放大器與低雜訊放大器 67
4.1 3~10GHz分散式串接單級放大器之設計與製作 67
4.1.1 設計流程 68
4.1.2 模擬與量測結果 69
4.1.3 結果與討論 75
4.2 3~10GHz分散式串接單級低雜訊放大器之設計與製作 77
4.1.1 設計流程 77
4.2.3 模擬與量測結果 78
4.2.3 結果與討論 83
第五章 UWB射頻前端晶片 84
5.1 3-10 GHz CMOS UWB射頻前端電路 84
5.1.1 電路架構 84
5.1.2 設計原理及流程 85
5.1.3 模擬與量測結果 88
5.1.4 結果討論 94
第六章 結論 95
參考文獻 97
附錄 A 102
功率放大器設計簡介[70] 102
A.1 功率放大器偏壓點選擇與分類 102
A.2 驅動級線性度之設計考量 105
A.3 以負載線理論(Load Line Theory)設計功率輸出級[70]-[72] 107
A.3 負載調整法(Load-Pull Method)[72] 113
附錄 B 分散式低雜訊放大器的雜訊指數簡介 118
附錄 C 3-10 GHz CMOS 串接單級分散式低雜訊放大器 123
C.1 UWB低雜訊放大器(1) 123
C.1.1 電路架構 123
C.1.2 設計原理及流程 124
C.1.3 模擬及量測結果 125
C.1.4 結果討論 127
C.2 UWB低雜訊放大器(2) 127
C.2.1 電路架構 127
C.2.2 設計原理及流程 128
C.2.3 模擬及量測結果 129
C.2.4 結果討論 131
C.3 UWB低雜訊放大器(3) 132
C.3.1 電路架構 132
C.3.2 設計原理及流程 132
C.3.3 模擬及量測結果 133
C.3.4 結果討論 136

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