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研究生:林展裕
研究生(外文):Jhan-Yu Lin
論文名稱:應用於DS-UWB接收機之CMOS4/8-GHz雙頻帶頻率合成器及射頻晶片的研究
論文名稱(外文):Research of CMOS 4/8-GHz Dual-Band Frequency Synthesizer and RFICs For DS-UWB Receiver
指導教授:盧春林盧春林引用關係莊惠如莊惠如引用關係
指導教授(外文):Chun-Lin LuHuey-Ru Chuang
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電腦與通信工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:中文
論文頁數:134
中文關鍵詞:頻率合成器射頻晶片超寬頻壓控振盪器
外文關鍵詞:RFICdual-bandVCOfrequency synthesizerDS-UWB
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  本論文以TSMC 0.18-μm 1P6M CMOS製程,設計研究應用於DS-UWB之射頻晶片,包含3-5-GHz低雜訊放大器、4/8-GHz雙頻壓控振盪器、4/8-GHz雙頻帶頻率合成器及整合晶片,RFIC晶片採用打鎊線至FR-4基板上進行量測。3-5-GHz低雜訊放大器量測,輸入及輸出返回損耗都在10 dB以上,增益為12.1-18.6 dB,input P1dB為-17.2- -26.7 dBm,IIP3為-11.2- -17.9 dBm,雜訊指數則小於5.48 dB。4/8-GHz雙頻壓控振盪器量測結果,在4 GHz時,輸出頻率為4154-4358 MHz,輸出功率大於0 dBm;而在8 GHz時,輸出頻率為8372-8747 MHz,輸出功率大於1.28 dBm。將頻率鎖定在4.3 GHz及8.6 GHz,相位雜訊在4.3 GHz時,量測結果-84.6 dBc/Hz@100-kHz offset;在8.6 GHz時,量測結果為-81.7 dBc/Hz@100-kHz offset。4/8-GHz雙頻頻率合成器量測,在4 GHz時,VCO輸出頻率4057-4242 MHz,輸出功率大於-4.53 dBm,鎖定在4.1 GHz時,相位雜訊-84.1 dBc/Hz@100-kHz offset;在8 GHz時,VCO輸出頻率8128-8556 MHz,輸出功率大於-4.38 dBm,鎖定在8.2 GHz時,相位雜訊-78.9 dBc/Hz@100-kHz offset。頻率合成器與混波器的整合電路,在量測上分成三個部分,頻率合成器的部分輸出頻率為4192-4376 MHz,輸出功率大於-7.46 dBm,相位雜訊為-88.7 dBc/Hz@100-kHz offset。而在混波器的量測結果轉換增益-0.9- -6.1 dB,input P1dB為-5.1- -8.8 dBm,IIP3為-2.6- 2.2 dBm,雜訊指數小於16.12 dB。前端電路包含低雜訊放大器、平衡器及混波器,量測結果增益為9.1-14.4 dB,input P1dB為-25.2- -16 dBm,IIP3為-16.7- -6.75 dBm,雜訊指數小於11.15 dB。而整合晶片之量測與部份操作功能特性及發生之問題,均有完整之討論。
  另外本論文設計802.11a及802.11b WLAN CMOS頻率合成器,其中頻率合成器架構、Motorola MC12210 IC簡介,模擬與量測結果將置於附錄中。
 This thesis presents the research on CMOS 3-5-GHz broadband LNA, 4/8-GHz dual-band VCO, 4/8-GHz dual-band frequency synthesizer, and integrated circuit RFICs for DS-UWB applications. The RFICs are fabricated in a TSMC standard 0.18-μm CMOS precess. The circuit measurement is performed using a FR-4 PCB test fixture. The 3-5-GHz broadband LNA exhibits a gain of 12.1-18.6 dB, input return loss and output return loss are higher than 10 dB, input P1dB is -17.2- -26.7 dBm, IIP3 is -11.2- -17.9 dBm, and noise figure is less than 5.48 dB. The 4/8-GHz dual-band VCO exhibits an output frequency from 4154 to 4358 MHz in low band, and from 8128 to 8556 MHz in high band. The dual-band VCO with divided-by-4 chip and Motorola MC12210 PLL chip form a frequency synthesizer. While output frequency locks at 4.3 GHz, the phase noise is -84.6 dBc/Hz@100-kHz offset, and locks at 8.6 GHz, the phase noise is -81.7 dBc/Hz@100-kHz offset. The dual-band frequency synthesizer includes dual-band VCO, phase/frequcney detector, charge pump and frequency divider. After modify the value of capacitor, the dual-band VCO can be locked in desired frequency. The frequency synthesizer and broadband mixer is integrated. In frequency synthesizer, the VCO output frequency is from 4192 to 4367 MHz. And when output frequency is locked in 4.3 GHz, the phase noise is -88.7 dBc/Hz@100-kHz offset. The broadband mixer exhibits a gain of -0.9- -6.1 dB, input P1dB is -5.1- -8.8 dBm, IIP3 is -2.6-2.2 dBm, and noise figure is less than 16.12 dB. The 3-5-GHz front-end includes LNA, active balun, and mixer, it exhibits a gain of 9.1-14.4 dB, input P1dB is -25.2 - -16 dBm, IIP3 is -16.7- -6.75 dBm, and noise figure is less than 11.15 dB. Detail measurement and each chip performance problem presented and discussed.
第一章 緒論 Introduction...............................................................1
  1.1 研究背景與動機.............................................................1
  1.2 UWB系統簡介................................................................2
  1.3 論文架構.........................................................................6

第二章 3-5-GHz CMOS寬頻低雜訊放大器.................................7
  2.1 低雜訊放大器基本架構.................................................7
  2.2 寬頻低雜訊放大器類型.................................................8
   2.2.1 柴比雪夫濾波器(Chebyshev filter)[5].......................8
   2.2.2 回授型寬頻放大器[6]............................................10
   2.2.3 共閘極型寬頻放大器[7]........................................11
  2.3 低雜訊放大器雜訊來源...............................................13
   2.3.1 電晶體雜訊來源....................................................13
   2.3.2 CMOS低雜訊放大器最佳化技術.........................15
  2.4 Bond-wire及pad..............................................................26
  2.5 3-5-GHz CMOS低雜訊放大器之研製..........................27
   2.5.1 電路架構................................................................27
   2.5.2 設計流程................................................................27
   2.5.3 模擬與量測............................................................29
   2.5.4 結果與討論............................................................32

第三章 4/8-GHz雙頻帶頻率合成器之設計...............................33
  3.1 頻率合成器架構與原理...............................................33
  3.2 鎖相迴路系統分析.......................................................34
  3.3 鎖相迴路雜訊...............................................................36
  3.4 4/8-GHz CMOS雙頻帶VCO之研製..............................39
   3.4.1 壓控振盪器原理與類型........................................39
   3.4.2 雙頻/寬頻VCO架構類型.......................................42
   3.4.3 設計與製作............................................................45
   3.4.4 模擬與量測結果....................................................48
   3.4.5 結果與討論............................................................53
  3.5 相頻偵測器設計...........................................................54
   3.5.1 相位偵測器原理....................................................54
   3.5.2 相頻偵測器設計與製作........................................56
   3.5.3 相頻偵測器模擬結果............................................57
  3.6 電荷幫浦設計...............................................................58
   3.6.1 電荷幫浦原理........................................................58
   3.6.2 電荷幫浦設計與製作............................................60
   3.6.3 電荷幫浦模擬結果................................................63
   3.6.4 相頻偵測器與電荷幫浦整體模擬結果...................64
  3.7 除頻器設計原理...........................................................66
   3.7.1 除5電路設計與製作..............................................67
   3.7.2 除4電路設計與製作..............................................69
   3.7.3 可程式化計數器設計與製作................................71
   3.7.4 除頻器模擬與量測結果........................................74
   3.7.5 結果與討論............................................................75
  3.8 4/8-GHz雙頻帶頻率合成器之研製..............................76
   3.8.1 雙頻VCO模擬與量測結果....................................76
   3.8.2 迴路濾波器設計....................................................79
   3.8.3 雙頻帶頻率合成器量測結果................................81
   3.8.4 結果與討論............................................................85

第四章 3-5-GHz CMOS整合電路..............................................87
  4.1 3-5-GHz寬頻混波器及4.1-GHz頻率合成器之研製....87
   4.1.1 電路架構考量........................................................87
   4.1.2 設計流程................................................................87
   4.1.3 模擬與量測結果....................................................91
   4.1.4 結果與討論............................................................97
  4.2 3-5-GHz CMOS前端電路之研製..................................97
   4.2.1 電路架構考量........................................................97
   4.2.2 設計流程................................................................98
   4.2.3 模擬與量測結果...................................................101
   4.2.4 結果與討論...........................................................104

第五章 結論...............................................................................105

參考文獻.......................................................................................107

附錄A L-C諧振振盪器相位雜訊..............................................109
  A.1 相位雜訊之定義.........................................................109
  A.2 相位雜訊模型.............................................................111

附錄B 2-GHz切換電容補償頻率偏移之頻率合成器..............115
  B.1 802.11 WLAN頻帶規畫...............................................115
  B.2 VCO電路架構.............................................................116
  B.3 2-GHz頻率合成器.......................................................118
  B.4 2-GHz VCO模擬與量測結果......................................120
  B.5 MC12210頻率合成器模組..........................................122
  B.6 結果與討論.................................................................126

附錄C 5-GHz CMOS頻率合成器..............................................127
  C.1 頻帶規畫.....................................................................127
  C.2 VCO電路架構.............................................................128
  C.3 5-GHz頻率合成器.......................................................129
  C.4 5-GHz VCO模擬與量測結果......................................130
  C.5 MC12210頻率合成器模組..........................................132
[1] http://www.ieee802.org/15/pub/TG3a.html
[2] K. Siwiak and D. McKeown, Ultra-wideband Radio Technology, John Wiley & Sons, 2004.
[3] G. R. Aiello and G. D. Rogerson, “Ultra-wideband wireless systems,” IEEE Microwave   Mag., vol. 4. pp. 36-47. Feb. 2003.
[4] 黃大榮,無線區域網路及數位電視寬頻調諧器之差動CMOS RFIC的研究設計,國立成功大學電機工程研究所碩士論文,民國九十三年。
[5] B.-Y. Yang, and C. F. Jou, “Design of a 3.1-10.6 GHz low-voltage, low power CMOS low-noise amplifier for ultra-wideband receivers,” Asia-Pacific Proceedings Microwave Conference APMC, vol. 2, Dec. 2005.
[6] C.-W. Kim, M.-S. Kang, P.-T. Anh, H.-T. Kim, and S.-G. Lee,“An ultra-wideband CMOS low noise amplifier for 3-5-GHz UWB system,” IEEE J. Solid-State Circuits, vol. 40, No. 2, pp. 544-547, Feb. 2005.
[7] X. Fan, S. S. Edgar, and S. M. Jose, “A 3 GHz-10 GHz common gate ultrawideband low noise amplifier,” Midwest Symposium on Circuit and System, pp. 631-634, Aug. 2005.
[8] T.-K. Nguyen, C.-H. Kim, G.-J. Ihm, M.-S. Yang, and S.-G. Lee, “CMOS low-noise amplifier design optimization techniques,” IEEE Trans. Microwave Theory Tech, vol. 52, No.5, pp. 1433-1442, May 2004.
[9] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge University Press, 1998.
[10] 郭信宏,應用於802.11 WLAN之2 GHz及5 GHz CMOS頻率合成器RFIC之設計研究,國立成功大學電機工程研究所碩士論文,民國九十三年。
[11] 林曉彤,應用於無線通訊之CMOS射頻微機電開關及2-GHz/5-GHz壓控振盪器RFIC之研究,國立成功大學電機工程研究所碩士論文,民國九十三年。
[12] H. Shin, Z. Xu and M. F. Chang, “A 1.8-V 6/9-GHz switchable dual-band quadrature LC VCO in SiGe BiCMOS technology,” IEEE J. Solid-State Circuits, vol.38, No. 6, pp. 1028-1032, June 2003.
[13] P. Andreani and S. Mattisson, “On the use of MOS varactors in RF VCO’s,” IEEE J. Solid-State Circuits, vol.35, No. 6, pp. 905-910, June 2000.
[14] R.-C. Chang and L.-C. Kuo, “A new low-voltage charge pump circuit for PLL,” IEEE International Symposium on Circuits and Systems ISCAS, vol. 5, pp. 701-703, May 2000.
[15] C.-Y. Yang et al., “New dynamic flip-flop for high-speed dual-modulus prescaler,” IEEE J. Solid-State Circuits, vol. 33, No. 10, pp. 1568-1571 Oct. 1998.
[16] S.-H. Lee and H.-J. Park, “A CMOS high-speed wide-range programmable counter,” IEEE trans. Circuits and Systems, vol. 49, no. 9, pp. 638-642 September 2002.
[17] C. Lam and B. Razavi, ”A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4- m CMOS technology,” IEEE J. Solid-State Circuits, vol.35, No. 5, pp. 788-794, May 2000.
[18] 袁杰,高頻通信電路設計-振盪電路相鎖環路及頻率合成器,全華書局,民國八十三年
[19] B. D. Muer, M. Borremans, M. Steyaert and G. L. puma, “A 2-GHz low-phase-noise integrated LC-VCO set with flicker-noise upconversion minimization,” IEEE J. Solid-State Circuit, vol. 35, No. 7, pp. 1034-1038, July 2000.
[20] A. Hajimiri and T. H. Lee, “Oscillator phase noise: a tutorial,” IEEE J. Solid-State Cireciut, vol. 32, No. 3, pp. 326-336, March 2000.
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