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研究生:王長鵬
研究生(外文):Chang-Peng Wang
論文名稱:適用於高解析度即時視訊處理之H.264/AVC去區塊效應濾波器架構設計
論文名稱(外文):An Architecture Design of De-blocking Filter in H.264/AVC for Real-time High Definition Video Processing
指導教授:陳中和陳中和引用關係
指導教授(外文):Chung-Ho Chen
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電腦與通信工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:英文
論文頁數:58
中文關鍵詞:區塊效應邊緣濾波器多媒體處理器
外文關鍵詞:edge filterblocking artifactmedia processor
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  在本篇論文裡,我們針對新視訊壓縮標準-H.264內嵌的適應性去區塊效應濾波器(in-loop adaptive de-blocking filter)-提供了一個高效能、五級管線化的架構。我們所提供的硬體架構,在處理一個巨集區塊(macro-block),包含一個16x16的亮度區塊(luminance block)及兩個8x8的彩度區塊(chrominance block),時僅需60個時脈週期。和先前所提出的硬體架構相比,我們的設計能在33MHz的運作時脈下,即時的處理1080P (1920 x 1080 @ 30fps) 的高解析度視訊影像。透過臺灣積體電路公司(TSMC)所提供的0.18 um標準元件庫(cell library)實現後,我們的設計能適當的運作在133 MHz的時脈下。現今的系統單晶片(system-on-chip)整合設計裡,系統匯流排(system bus)頻寬不足的問題急待解決,我們在設計之初,便將匯流排頻寬問題納入設計考量,因此,我們的所提供的數位矽智產(IP)將更有利於系統整合。
  This thesis presents a high performance five-stage pipelined architecture of the adaptive de-blocking filter adopted in the H.264/AVC codec. Using the proposed architecture, the processing cycles of each macro-block including one 16x16 luminance and two 8x8 chrominance blocks are only 60. Compared with previous works, our design can easily achieve the real-time processing with 1080P HD-DVD (1920x1080@30fps) resolution video sequences while the working frequency is only 33 MHz. Implemented with the 0.18 um technology, the design can operate at 133 MHz properly. In a modern system-on-chip design, the system bus bandwidth is a major problem. We had taken the bus utilization problem into consideration, and therefore our design is easier to be integrated into a multiple IPs system than previous works.
〔 Contents 〕
摘要                              III
Abstract                             IV
Acknowledgements                         V
Contents                             VI
Table Index                           VIII
Figure Index                           IX
Chapter 1 Introduction                      1
1.1 Motivation                          1
1.2 Contributions of This Thesis                   4
1.3 Thesis Organization                      4
Chapter 2 Related Works                     5
2.1 Algorithm of in-loop Adaptive De-blocking Filter           5
2.1.1 Overview                          5
2.1.2 Slice Level Adaptive                     7
2.1.3 Edge Level Adaptive                     7
2.1.4 Sample Level Adaptive                    8
2.1.5 Four Types of Filters                     9
2.2 Previous Works                        12
Chapter 3 Proposed Architecture                 13
3.1 Processing Order                       13
3.2 Five-stage Pipelined Architecture                 15
3.3 Adjacent Blocks                        17
Chapter 4  Implementation                    19
4.1 Software                           19
4.1.1 Overview                          19
4.1.2 De-blocking Filter                      20
4.1.3 External Memory Controller                  21
4.2 Hardware                           25
4.2.1 Overview                          25
4.2.2 The Pipeline Scheduling and the Finite State Machine         27
4.2.3 Edge Processing Unit                      36
4.2.4 Transposing Unit                       37
4.2.5 The Input Data Format                     38
4.2.6 The Output Data Format                    43
Chapter 5 Verification                       45
5.1 Overview                           45
5.2 Software                           46
5.3 Hardware                           48
5.3.1 Environment                         48
5.3.2 Verification Scheme                      48
5.3.3 Verification Result                      50
Chapter 6 Results and Analysis                   51
6.1 Experimental Results                      51
6.2 Analysis                           51
6.2.1 Comparison of Hardware Performance              51
6.2.2 Comparison of Local Memory Usage               52
6.2.3 Comparison between proposed I and proposed II implementations   53
Chapter 7 Conclusion                       54
References                            55
Vita                               58
----------------------------------


〔 Table Index 〕
Table 1-1 The most time-consumed components in H.264/AVC BP decoder.   3
Table 4-1 Statistics of SDRAM read/write times using the Open-Page-Policy.  22
Table 4-2 Statistics of SDRAM read/write times using the Close-Page-Policy.  22
Table 4-3 External Memory Addressing Ability.              23
Table 4-4 System bus usage in the MHAS.                24
Table 5-1 Verification results.                     50
Table 6-1 Comparisons with various designs operated @ 33MHz PCI bus.   51
----------------------------------


〔 Figure Index 〕
Figure 1-1 Revolution of digital video standards proposed by ITU-T and ISO/IEC. 1
Figure 1-2 Overview of the H.264/AVC encoder.              2
Figure 1-3 Overview of the H.264/AVC decoder.              2
Figure 2-1 Overview of the H.264/AVC in-loop de-blocking filter.       6
Figure 2-2 The four vertical and four horizontal edges in a MB.        6
Figure 2-3 Generation flow for the five BS values.             8
Figure 2-4 One line of pixels, p3~q3, with an actual edge between p0 and q0.   9
Figure 2-5 The filters decision flow.                  10
Figure 3-1 The standard processing order.                13
Figure 3-2 The rules of the filtering order defined by H.264/AVC.      14
Figure 3-3 Proposed processing order.                 15
Figure 3-4 Proposed five-stage pipelined architecture.           16
Figure 3-5 The left and the upper adjacent blocks.            18
Figure 4-1 Overview of the MHAS.                  20
Figure 4-2 The interface and architecture of the de-blocking filter in the MHAS. 20
Figure 4-3 Overview of 4 parallel processing pipelines for the luminance blocks. 26
Figure 4-4 Overview of 2 parallel processing pipelines for the chrominance blocks.26
Figure 4-5 The luminance data processing schedule.            27
Figure 4-6 The chrominance data processing schedule.           32
Figure 4-7 The vertical edge processing unit.               36
Figure 4-8 The horizontal edge processing unit.              37
Figure 4-9 Abstract of the transposition.                38
Figure 4-10 The block sequence defined by integer transformation.      38
Figure 4-11 The block sequence used in the proposed hardware accelerator.   39
Figure 4-12 The address swapping of reconstructed data buffer.       39
Figure 4-13 The original input sequence of the reconstructed data.      40
Figure 4-14 Data content of the 6 SP 16x32 RecBufs after address swapping.  41
Figure 4-15 The data content of 2 SP 16x32 TPBufs.           42
Figure 4-16 The 32 BS values.                    43
Figure 4-17 Overview of the output data schedule.            43
Figure 4-18 Details of the output data schedule.             44
Figure 5-1 The progressive HW/SW co-design flow.            46
Figure 5-2 The interface of the MHAS.                 47
Figure 5-3 Performance of MHAS v.s. JM 7.3 in football_cif 90 frames(1I,89P).47
Figure 5-4 The development and verification board we used.        48
Figure 5-5 HW/SW co-verification scheme.               49
Figure 5-6 Software aided system verification scheme.           49
----------------------------------
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available: http://iphome.hhi.de/suehring/tml/.
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