臺灣博碩士論文加值系統

本論文分為三部份，其中研製之RFIC皆應用於DS-UWB收發機之中，第一部份為研製應用於DS-UWB接收機之3-5-GHz及6-10-GHz寬頻CMOS低雜訊放大器RFIC。第二部份為研製應用於DS-UWB接收機之3-5-GHz及6-10-GHz寬頻CMOS折疊式混波器RFIC。第三部份為研製應用於DS-UWB發射機之3-5-GHz及6-10-GHz寬頻CMOS發射放大器RFIC。第一及第二部份研製之RFIC使用TSMC 0.18-μm 1P6M CMOS製程，第三部份研製之RFIC則使用UMC 0.18-μm 1P6M CMOS 製程。應用於3-5-GHz頻帶之所有RFIC晶片，皆採用打鎊線至FR-4基板上量測；應用於6-10-GHz頻帶之所有RFIC晶片，皆採用on-wafer方式量測。
3-5-GHz寬頻CMOS低雜訊放大器，電路以一共源極電晶體與緩衝器串接而組成，量測結果增益為7.1-9 dB、雜訊指數為4.8-6.1 dB。6-10-GHz寬頻CMOS低雜訊放大器以單級疊接放大器及串接兩級疊接放大器實現，量測結果增益為6-8.4 dB、雜訊指數為4.6-5.1 dB；增益為11-13.8 dB、雜訊指數為5.3-6.2 dB。3-5-GHz寬頻CMOS折疊式混波器，量測結果LO power僅需要-10 dBm、轉換增益為3.8-6.9 dB @ 3 -3.99 GHz & 1.5-4.8 dB @ 4.01-5 GHz、input P1dB為-16.7- -15.1 dBm @ 3-3.99 GHz & -15.2- -12 dBm @ 4.01-5 GHz、LO-RF isolation 33.8 dB。6-10-GHz寬頻CMOS折疊式混波器，量測結果LO power僅需要-3 dBm、轉換增益為-1.8-0.8 dB @ 6 - 7.9 GHz & -3.3- -0.4 dB @ 8.1-10 GHz、input P1dB -6 dBm @ 6-7.9 GHz & -4 dBm @ 8.1-10 GHz、LO-RF isolation 30 dB。2.6-4.6-GHz寬頻CMOS發射放大器，量測結果小訊號增益為9.2-11.9 dB，OP1dB為-3.4-0.3 dBm、PAE為5.8-13.9% @ OP1dB、η為6.1-14.3% @ OP1dB。6-10-GHz寬頻CMOS發射放大器，量測結果小訊號增益為7.6-10.5 dB、OP1dB為2.8- 6.1 dBm、PAE為8.8-17.6% @ OP1dB、η為9.7-21.1% @ OP1dB。

This thesis divides into three parts, all designed RFICs applied to DS-UWB transceiver is included. The first part presents 3-5-GHz and 6-10-GHz broadband CMOS low noise amplifier, the second part is 3-5-GHz and 6-10-GHz broadband CMOS folded-cascode mixer, and the third part is 3-5-GHz and 6-10-GHz broadband CMOS transmitting amplifier. The RFICs included in the first and the second part are designed on TSMC 0.18-μm 1P6M CMOS process, and the third part is on UMC 0.18-μm 1P6M CMOS process. The RFICs applied to 3-5-GHz band is measured on FR-4 PC board, and for 6-10-GHz band is on wafer.
3-5-GHz broadband CMOS low noise amplifier is the combination of a common-source transistor and a buffer. Measured results show a noise figure of 4.8 -6.1 dB, and a gain of 7.1-9 dB. 6-10-GHz broadband CMOS low noise amplifier is implemented by two topologies, respectively: Only one single-stage cascode amplifier, and two single-stage cascode amplifier cascaded. Measured results exhibit a noise figure of 4.6 -5.1 dB, and a gain of 6-8.4 dB; the other is a noise figure of 5.3-6.2 dB, and a gain of 11-13.8 dB. 3-5-GHz broadband CMOS folded-cascode mixer is measured as a conversion gain of -1.5-2.5 dB @ 3 -3.99 GHz & -2.6 -0.9 dB @ 4.01-5 GHz, an input P1dB of -9.5- -10.5 dBm @ 3-3.99 GHz & -8.5- -7.5 dBm @ 4.01-5 GHz, a LO-RF isolation of 33.8 dB, and the required LO power is only -10 dBm. 6-10-GHz broadband CMOS folded-mirror mixer is measured as a conversion gain of -1.8-0.8 dB @ 6 - 7.9 GHz & -3.3- -0.4 dB @ 8.1-10 GHz, and an input P1dB ~ -6 dBm @ 6-7.9 GHz & -4 dBm @ 8.1-10 GHz, a LO-RF isolation of 30 dB, and the required LO power is only -3 dBm. 2.6-4.6-GHz broadband CMOS TA is measured as a small signal gain of 9.2-11.9 dB, an OP1dB of -3.4- 0.3 dBm, a PAE of 5.8-13.9% @ OP1dB, and aηof 6.1-14.3% @ OP1dB. 6-10-GHz broadband CMOS TA is measured as a small signal gain of 7.6-10.5 dB, an OP1dB of 2.8-6.1 dBm, a PAE of 8.8-17.6% @ OP1dB, and ηof 9.7-21.1% @ OP1dB.

目錄

第一章 序論 Introduction 1

1.1 超寬頻(UWB)研究背景與動機 1
1.2 超寬頻基本原理 1
1.3 超寬頻頻帶配置 3
1.4 DS-CDMA超寬頻系統鏈路計算 4
1.5 論文架構 8

第二章 寬頻輸入、輸出匹配電路及電路線性度之探討 10

2.1 輸入匹配網路/電路之探討 10
2.1.1 濾波器型式匹配網路 10
2.1.2 主動匹配電路 11
2.2 輸出匹配網路/電路之探討 13
2.2.1 、 與S11、S22 14
2.2.2 源極隨耦器 15
2.2.3 低Q值電感性負載之共源極緩衝器 18
2.2.4 電阻性負載之共源極緩衝器 23
2.3 電路線性度之探討 24
2.3.1 不同型態偏壓元件之電壓及電流擺幅比較 25
2.3.2 討論 28

第三章 寬頻CMOS低雜訊放大器 (TSMC 0.18 μm) 29

3.1 低雜訊放大器(LNA)之簡介 29
3.2 3-5-GHz寬頻CMOS低雜訊放大器 30
3.2.1 電路架構考量 30
3.2.2 源極退化電感選擇 30
3.2.3 放大電晶體最佳寬度選擇 34
3.2.4 輸出阻抗匹配考量 36
3.2.5 寬頻放大器之分析 36
3.2.6 輸入阻抗匹配之分析 38
3.2.7 完整電路設計考量 40
3.2.8 模擬與量測結果 41
3.2.9 結果討論 44
3.3 6-10-GHz寬頻CMOS單級疊接式低雜訊放大器 44
3.3.1 電路架構考量 44
3.3.2 源極退化電感選擇 45
3.3.3 放大電晶體最佳寬度選擇 45
3.3.4 疊接電晶體適當寬度選擇 46
3.3.5 輸入匹配網路設計 50
3.3.6 考量輸出匹配網路之輸出阻抗分析 52
3.3.7 疊接放大器等效轉導分析 53
3.3.8 穩定電路及增益平坦化考量 55
3.3.9 輸出匹配網路設計 60
3.3.10 完整電路設計與考量 61
3.3.11 模擬與量測結果 62
3.3.12 結果討論 64
3.4 6-10-GHz寬頻CMOS低雜訊放大器 65
3.4.1 並聯L-C諧振之探討 65
3.4.2 寬頻電路架構實現 68
3.4.3 串接雜訊因數 69
3.4.4 第一級電路等效雜訊指數相關分析 72
3.4.5 第二級電路等效雜訊指數相關分析 73
3.4.6 第三級電路等效雜訊指數相關分析 79
3.4.7 電路級間寄生電容對雜訊指數影響之分析 81
3.4.8 完整電路設計與考量 82
3.4.9 模擬與量測結果 84
3.4.10 結果與討論 86

第四章 寬頻CMOS折疊式混波器 (TSMC 0.18 μm) 87

4.1 混波器原理與設計相關考量 87
4.2 混波器架構探討 89
4.3 3-5-GHz寬頻CMOS折疊式混波器 91
4.3.1 3-5-GHz寬頻混波器架構之實現 91
4.3.2 RF、LO及IF port 三端型態考量 92
4.3.3 RF端balun設計及阻抗匹配考量 93
4.3.4 Load1及M1、M2寬度之選擇與考量 96
4.3.5 切換開關之動作原理 97
4.3.6 切換開關顫抖雜訊之影響 97
4.3.7 LO端阻抗匹配之考量 99
4.3.8 Load2與輸出緩衝器之選擇與考量 101
4.3.9 轉換增益之分析 102
4.3.10 模擬與量測結果 104
4.3.11 結果討論 107
4.4 6-10-GHz寬頻CMOS折疊式電流鏡混波器 108
4.4.1 寬頻化電路操作頻寬 109
4.4.2 輸出端balun分析 112
4.4.3 模擬與量測結果 114
4.4.4 結果討論 117

第五章 寬頻CMOS發射放大器 (UMC 0.18 μm) 118

5.1 發射放大器之相關特性參數 118
5.2 發射放大器之電路架構考量 119
5.2.1 高輸出功率之功率放大器相關討論 119
5.2.2 應用於DS-UWB之發射放大器相關考量 120
5.2.3 PA及TA之差異 120
5.2.4 發射放大器電路架構考量 121
5.3 3-5-GHz寬頻CMOS中間級電感補償式發射放大器 122
5.3.1 小訊號放大器設計相關考量 122
5.3.2 驅動放大器設計相關考量 122
5.3.3 中間級電感補償式網路設計考量 123
5.3.4 輸出匹配網路設計 123
5.3.5 模擬與量測結果 125
5.3.6 結果討論 127_Toc144450232
5.4 6-10-GHz寬頻CMOS中間級阻抗轉換式發射放大器 127
5.4.1 小訊號放大器之設計 127
5.4.2 驅動放大器之設計 128
5.4.3 中間級阻抗轉換網路之設計 129
5.4.4 輸出阻抗匹配網路之設計 137
5.4.5 小訊號放大器增益及Zintr之回顧 141
5.4.6 完整電路之設計與相關考量 143
5.4.7 模擬與量測結果 143
5.4.8 結果討論 146

第六章 結論 147

參考文獻 149

附錄A 疊接放大器之輸入阻抗分析 (考量閘汲極寄生電容) 152

附錄B 疊接放大器之閘-源極壓降分析(考量閘汲極寄生電容) 155

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